参数资料
| 型号： | AD5024BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/28页 |
| 文件大小： | 0K |
| 描述： | IC DAC QUAD 12BIT 1LSB 16-TSSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 系列： | nanoDAC™ |
| 设置时间： | 8µs |
| 位数： | 12 |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 4 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 30mW |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
| 输出数目和类型： | 4 电压，双极 |
| 采样率（每秒）： | 125k |
| 产品目录页面： | 781 (CN2011-ZH PDF) |
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Data Sheet
AD5024/AD5044/AD5064
Rev. F | Page 25 of 28
MICROPROCESSOR INTERFACING
AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSP-
BF53x Interface
Figure 52 shows a serial interface between the AD5024/AD5044/
AD5064/AD5064-1 and the Blackfin ADSP-BF53x microproces-
sor. The ADSP-BF53x processor family incorporates two dual-
channel synchronous serial ports, SPORT1 and SPORT0, for
serial and multiprocessor communications. Using SPORT0 to
connect to the AD5024/AD5044/AD5064/AD5064-1, the setup
for the interface is as follows: DT0PRI drives the DIN pin of the
AD5024/AD5044/AD5064/AD5064-1, and TSCLK0 drives the
SCLK of the parts. The SYNC pin is driven from TFS0.
AD5024/
AD5044/
AD5064/
AD5064-1*
ADSP-BF53x*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
TFS0
DIN
DT0PRI
SCLK
TSCLK0
06803-
012
Figure 52. AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSP-BF53x
Interface
AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11
Interface
Figure 53 shows a serial interface between the AD5024/AD5044/
AD5064/AD5064-1 and the 68HC11/68L11 microcontroller.
SCK of the 68HC11/68L11 drives the SCLK of the AD5024/
AD5044/AD5064/AD5064-1, and the MOSI output drives the
serial data line of the DAC.
AD5024/
AD5044/
AD5064/
AD5064-1*
68HC11/68L11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SYNC
PC7
SCLK
SCK
DIN
MOSI
06803-
013
Figure 53. AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11 Interface
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
The 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SYNC line is taken low (PC7). When the 68HC11/68L11 is
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5024/AD5044/
AD5064, PC7 is left low after the first eight bits are transferred,
and a second serial write operation is performed to the DAC.
PC7 is taken high at the end of this procedure.
AD5024/AD5044/AD5064/AD5064-1 to 80C51/80L51
Interface
Figure 54 shows a serial interface between the AD5024/AD5044/
AD5064/AD5064-1 and the 80C51/80L51 microcontroller. The
setup for the interface is as follows: TxD of the 80C51/80L51
drives SCLK of the AD5024/AD5044/AD5064/AD5064-1, and
RxD drives the serial data line of the part. The SYNC signal is
again derived from a bit-programmable pin on the port. In this
case, Port Line P3.3 is used. When data is to be transmitted to the
AD5024/AD5044/AD5064/AD5064-1, P3.3 is taken low. The
80C51/80L51 transmit data in 8-bit bytes only; thus, only eight
falling clock edges occur in the transmit cycle. To load data to
the DAC, P3.3 is left low after the first eight bits are transmitted,
and a second write cycle is initiated to transmit the second byte of
data. P3.3 is taken high following the completion of this cycle.
The 80C51/80L51 output the serial data in a format that has the
LSB first. The AD5024/AD5044/AD5064/AD5064-1 must
receive data with the MSB first. The 80C51/80L51 transmit
routine should take this into account.
AD5024/
AD5044/
AD5064/
AD5064-1*
*ADDITIONAL PINS OMITTED FOR CLARITY.
DIN
RxD
SYNC
P3.3
80C51/80L51*
SCLK
TxD
06803-
014
Figure 54. AD5024/AD5044/AD5064/AD5064-1 to 80C512/80L51 Interface
AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE
Interface
Figure 55 shows an interface between the AD5024/AD5044/
AD5064/AD5064-1 and any MICROWIRE-compatible device.
Serial data is shifted out on the falling edge of the serial clock and is
clocked into the AD5024/AD5044/AD5064/AD5064-1 on the
rising edge of the SCLK.
AD5024/
AD5044/
AD5064/
AD5064-1*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK
SO
SYNC
CS
MICROWIRE*
DIN
SK
06803-
015
Figure 55. AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE Interface
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5024BRUZ-REEL7 | 功能描述:IC DAC 12BIT QUAD SPI 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:nanoDAC™ 标准包装:47 系列:- 设置时间:2µs 位数:14 数据接口:并联 转换器数目:1 电压电源:单电源 功率耗散（最大）:55µW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:管件 输出数目和类型:1 电流，单极；1 电流，双极 采样率（每秒）:* |
| AD5024HB-C71 | 制造商:ADDA Corporation 功能描述:DC-FAN, 50X50X20 MM, 24 VOLTS, |
| AD5024HB-D71 | 功能描述:鼓风机 50mm 24VDC 12CFM RoHS:否 制造商:Murata 产品:Blowers 电流类型:DC 电源电压:5.3 V 气流:1 l/min 轴承类型: 噪声: 速度: 功率额定值: 框架尺寸 (mm):20 mm x 20 mm x 1.85 mm 外壳材料: 端接类型:SMD/SMT 系列:MZB |
| AD5024HB-D71-LF | 功能描述:风扇 50mm 24VDC 12CFM RoHS:否 制造商:Sanyo Denki 产品:Fans 电流类型: 电源电压:48 V 气流:636 CFM 轴承类型: 噪声:83 dBA 速度:6400 RPM 功率额定值:264 W 框架尺寸 (mm):172 mm x 150 mm x 102 mm 外壳材料:Aluminum 端接类型:Wire 系列: |
| AD5024LB-C71 | 制造商:ADDA Corporation 功能描述:DC-FAN, 50X50X20 MM, 24 VOLTS, |
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