参数资料
型号: AD5111BCPZ10-RL7
厂商: Analog Devices Inc
文件页数: 14/24页
文件大小: 0K
描述: IC DGTL POT 128POS 10K 8LFCSP
标准包装: 1
接片: 128
电阻(欧姆): 10k
电路数: 1
温度系数: 标准值 35 ppm/°C
存储器类型: 非易失
接口: 3 线串行(芯片选择,增/减)
电源电压: 2.3 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-UFDFN 裸露焊盘,CSP
供应商设备封装: 8-LFCSP-UD(2x2)
包装: 标准包装
其它名称: AD5111BCPZ10-RL7DKR
Data Sheet
AD5111/AD5113/AD5115
Rev. | Page 21 of 24
POWER-UP SEQUENCE
Because of the ESD protection diodes that limit the voltage
compliance at the A, B, and W terminals (see Figure 45), it is
important to power on VDD before applying any voltage to the
A, B, and W terminals. Otherwise, the diodes are forward-
biased such that VDD is powered on unintentionally and can
affect other parts of the circuit. Similarly, VDD should be
powered down last. The ideal power-on sequence is in the
following order: GND, VDD, and VA/VB/VW. The order of
powering VA, VB, VW and the digital inputs is not important as
long as they are powered on after VDD.
GND
VDD
A
W
B
09654-
046
Figure 45. Maximum Terminal Voltages Set by VDD and GND
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use compact, minimum lead
length layout design. The leads to the input should be as direct
as possible with a minimum conductor length. Ground paths
should have low resistance and low inductance. It is also good
practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 μF to 10 μF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 46 illustrates the basic supply bypassing configuration
VDD
+
GND
C1
0.1F
C2
10F
AGND
AD5111/
AD5113/
AD5115
09654-
047
Figure 46. Power Supply Bypassing
A
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