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参数资料
| 型号： | AD5175BRMZ-10-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/20页 |
| 文件大小： | 0K |
| 描述： | IC DGTL POT 1024POS 10K 10MSOP |
| 标准包装： | 1,000 |
| 接片： | 1024 |
| 电阻（欧姆）： | 10k |
| 电路数： | 1 |
| 温度系数： | 标准值 35 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | I²C |
| 电源电压： | 2.7 V ~ 5.5 V，±2.5 V ~ 2.75 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
AD5175
Rev. A | Page 12 of 20
THEORY OF OPERATION
The AD5175 is designed to operate as a true variable resistor for
analog signals within the terminal voltage range of VSS < VTERM
< VDD. The RDAC register contents determine the resistor wiper
position. The RDAC register acts as a scratchpad register, which
allows unlimited changes of resistance settings. The RDAC
register can be programmed with any position setting using
the I2C interface. When a desirable wiper position is found, this
value can be stored in a 50-TP memory register. Thereafter, the
wiper position is always restored to that position for subsequent
power-up. The storing of 50-TP data takes approximately 350 ms;
during this time, the AD5175 is locked and does not acknowl-
edge any new command thereby preventing any changes from
taking place. The acknowledge bit can be polled to verify that
the fuse program command is complete.
SERIAL DATA INTERFACE
The AD5175 has a 2-wire I2C-compatible serial interface.
It can be connected to an I2C bus as a slave device under the
control of a master device; see Figure 3 for a timing diagram
of a typical write sequence.
The AD5175 supports standard (100 kHz) and fast (400 kHz)
data transfer modes. Support is not provided for 10-bit
addressing and general call addressing.
The AD5175 has a 7-bit slave address. The five MSBs are 01011
and the two LSBs are determined by the state of the ADDR pin.
The facility to make hardwired changes to ADDR allows the
user to incorporate up to three of these devices on one bus, as
outlined in Table 6.
The 2-wire serial bus protocol operates as follows: The master
initiates a data transfer by establishing a start condition, which
is when a high-to-low transition on the SDA line occurs while
SCL is high. The next byte is the address byte, which consists
of the 7-bit slave address and a R/W bit. The slave device
corresponding to the transmitted address responds by pulling
SDA low during the ninth clock pulse (this is termed the acknowl-
edge bit). At this stage, all other devices on the bus remain idle
while the selected device waits for data to be written to, or read
from, its shift register.
Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.
When all data bits have been read or written, a stop condition is
established. In write mode, the master pulls the SDA line high
during the 10th clock pulse to establish a stop condition. In read
mode, the master issues a no acknowledge for the ninth clock
pulse, that is, the SDA line remains high. The master then
brings the SDA line low before the 10th clock pulse, and then
high during the 10th clock pulse to establish a stop condition.
SHIFT REGISTER
For the AD5175, the shift register is 16 bits wide, as shown in
Figure 2. The 16-bit word consists of two unused bits, which
should be set to 0, followed by four control bits and 10 RDAC data
bits, and data is loaded MSB first (Bit D9). The four control bits
determine the function of the software command (Table 7).
Figure 25 shows a timing diagram of a typical AD5175 write
sequence.
The command bits (Cx) control the operation of the digital
potentiometer and the internal 50-TP memory. The data bits
(Dx) are the values that are loaded into the decoded register.
Table 6. Device Address Selection
ADDR Pin
A1
A0
7-Bit I2C Device Address
GND
1
0101111
VDD
0
0101100
NC (No Connection)1
1
0
0101110
1 Not available in bipolar mode. VSS < 0 V.
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