AD5245
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and
instructing the part only once. During the write cycle, each data
byte will update the RDAC output. For example, after the RDAC
has acknowledged its slave address and instruction bytes, the
RDAC output will update after these two bytes. If another byte
is written to the RDAC while it is still addressed to a specific
slave device with the same instruction, this byte will update the
output of the selected slave device. If different instructions are
needed, the write mode has to start again with a new slave
address, instruction, and data byte. Similarly, a repeated read
function of the RDAC is also allowed.
Readback RDAC Value
The AD5245 allows the user to read back the RDAC values in
the read mode. Refer to Table 5 and Table 6 for the
programming format.
Multiple Devices on One Bus
Figure 40 shows two AD5245 devices on the same serial bus.
Each has a different slave address since the states of their AD0
pins are different. This allows each RDAC within each device to
be written to or read from independently. The master device
output bus line drivers are open-drain pull-downs in a fully I
2
C
compatible interface.
MASTER
AD5245
SDA SCL
R
P
R
P
+5V
+5V
SDA
SCL
SDA SCL
AD5245
AD0
AD0
Figure 40. Multiple AD5245 Devices on One I
2
C Bus
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems may be operated at one voltage, a
new component may be optimized at another. When two
systems operate the same signal at two different voltages, proper
level shifting is needed. For instance, one can use a 3.3 V
E
2
PROM to interface with a 5 V digital potentiometer. A level
shifting scheme is needed to enable a bidirectional
communication so that the setting of the digital potentiometer
can be stored to and retrieved from the E
2
PROM. Figure 41
shows one of the implementations. M1 and M2 can be any
N-channel signal FETs, or if V
DD
falls below 2.5 V, low threshold
FETs such as the FDV301N.
E
2
PROM
AD5245
SDA1
SCL1
D
G
R
P
R
P
3.3V
5V
S
M1
SCL2
SDA2
R
P
R
P
G
S
M2
V
DD1
= 3.3V
V
DD2=
5V
D
Figure 41. Level Shifting for Operation at Different Potentials
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 42 and Figure 43.
This applies to the digital input pins SDA, SCL, and AD0.
LOGIC
340
V
SS
Figure 42. ESD Protection of Digital Pins
A,B,W
V
SS
Figure 43. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5245 V
DD
and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on terminals A, B, and W that
exceed V
DD
or GND will be clamped by the internal forward
biased diodes (see Figure 44).
A
V
DD
B
W
V
SS
Figure 44. Maximum Terminal Voltages Set by V
DD
and V
SS
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