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参数资料
| 型号： | AD5245BRJ50-RL7 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字电位计 |
| 英文描述： | 256-Position I2C Compatible Digital Potentiometer |
| 中文描述： | 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO8 |
| 封装： | 2.90 X 3 MM, MO-178BA, SOT-23, 8 PIN |
| 文件页数： | 5/16页 |
| 文件大小： | 995K |
| 代理商： | AD5245BRJ50-RL7 |
AD5245
TIMING CHARACTERISTICS—5 k, 10 k, 50 k, 100 k VERSIONS
(V
DD
= +5V ± 10%, or +3V ± 10%; V
A
= V
DD
; V
B
= 0 V; –40°C < T
A
< +125°C; unless otherwise noted.)
Table 3.
Parameter
Symbol
I
2
C INTERFACE TIMING CHARACTERISTICS
6, 10
(Specifications Apply to All Parts)
SCL Clock Frequency
f
SCL
t
BUF
Bus Free Time between STOP and START
t
1
t
HD;STA
Hold Time (Repeated START)
t
2
Conditions
Min
1.3
0.6
Typ
1
Max
400
Unit
kHz
μs
μs
After this period, the first clock pulse is
generated.
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time for Repeated START Condition
t
HD;DAT
Data Hold Time
t
SU;DAT
Data Setup Time
t
F
Fall Time of Both SDA and SCL Signals
t
R
Rise Time of Both SDA and SCL Signals
t
SU;STO
Setup Time for STOP Condition
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
1.3
0.6
0.6
100
0.6
50
0.9
300
300
μs
μs
μs
μs
ns
ns
ns
μs
NOTES
1
Typical specifications represent average readings at +25°C and V
DD
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, Wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V
DD
and V
B
= 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use V
DD
= 5 V.
10
See timing diagrams for locations of measured values.
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25°C, unless otherwise noted.)
Table 4.
Parameter
V
DD
to GND
V
A
, V
B
, V
W
to GND
I
MAX1
Digital Inputs and Output Voltage to GND
Operating Temperature Range
Maximum Junction Temperature (T
JMAX
)
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Thermal Resistance
2
θ
JA
: MSOP-10
NOTES
1
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Package power dissipation = (T
JMAX
– T
A
)/θ
JA
.
Value
–0.3 V to +7 V
V
DD
±20 mA
0 V to +7 V
–40°C to +125°C
150°C
–65°C to +150°C
300°C
230°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 5 of 16
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