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参数资料
| 型号： | AD5274BCPZ-20-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/28页 |
| 文件大小： | 0K |
| 描述： | IC RHEOSTAT 5V 50-TP 256 10MSOP |
| 标准包装： | 1 |
| 接片： | 256 |
| 电阻（欧姆）： | 20k |
| 电路数： | 1 |
| 温度系数： | 标准值 5 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | I²C |
| 电源电压： | 2.7 V ~ 5.5 V，±2.5 V ~ 2.75 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 标准包装 |
| 其它名称： | AD5274BCPZ-20-RL7DKR |
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Data Sheet
AD5272/AD5274
Rev. D | Page 21 of 28
RDAC REGISTER
The RDAC register directly controls the position of the digital
rheostat wiper. For example, when the RDAC register is loaded
with all zeros, the wiper is connected to Terminal A of the
variable resistor. It is possible to both write to and read from
the RDAC register using the I2C interface. The RDAC register
is a standard logic register; there is no restriction on the number
of changes allowed.
50-TP MEMORY BLOCK
The AD5272/AD5274 contain an array of 50-TP programmable
memory registers, which allow the wiper position to be pro-
grammed up to 50 times. Table 16 shows the memory map.
Command 3 in Table 12 programs the contents of the RDAC
register to memory. The first address to be programmed is
Location 0x01, see Table 16, and the AD5272/AD5274 incre-
ments the 50-TP memory address for each subsequent program
until the memory is full. Programming data to 50-TP consumes
approximately 4 mA for 55 ms, and takes approximately 350 ms
to complete, during which time the shift register is locked pre-
venting any changes from taking place. Bit C3 of the control
register in Table 15 can be polled to verify that the fuse program
command was successful. No change in supply voltage is required
to program the 50-TP memory; however, a 1 F capacitor on
the EXT_CAP pin is required as shown in Figure 47.
Prior to 50-TP activation, the AD5272/AD5274 is preset to
midscale on power-up. It is possible to read back the contents
of any of the 50-TP memory registers through the I2C interface
by using Command 5 in Table 12. The lower six LSB bits, D0 to
D5 of the data byte, select which memory location is to be read
back. A binary encoded version address of the most recently
programmed wiper memory location can be read back using
Command 6 in Table 12. This can be used to monitor the spare
memory status of the 50-TP memory block.
WRITE PROTECTION
On power-up, serial data input register write commands for
both the RDAC register and the 50-TP memory registers are
disabled. The RDAC write protect bit (Bit C1) of the control
register (see Table 14 and Table 15) is set to 0 by default. This
disables any change of the RDAC register content regardless of
the software commands, except that the RDAC register can be
refreshed from the 50-TP memory using the software reset,
Command 4, or through hardware by the RESET pin. To enable
programming of the variable resistor wiper position (programming
the RDAC register), the write protect bit (Bit C1) of the control
register must first be programmed. This is accomplished by
loading the serial data input register with Command 7 (see
Table 12). To enable programming of the 50-TP memory block,
Bit C0 of the control register, which is set to 0 by default, must
first be set to 1.
Table 12. Command Operation Truth Table
Command
Number
Command[DB13:DB10]
Data[DB9:B0]1
C3
C2
C1
C0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
X
NOP: do nothing.
1
0
1
D9
D8
D7
D6
D5
D4
D3
D2
Write contents of serial register
data to RDAC.
2
0
1
0
X
Read contents of RDAC wiper
register.
3
0
1
X
Store wiper setting: store RDAC
setting to 50-TP.
4
0
1
0
X
Software reset: refresh RDAC
with the last 50-TP memory
stored value.
0
1
0
1
X
D5
D4
D3
D2
D1
D0
Read contents of 50-TP from the
SDO output in the next frame.
6
0
1
0
X
Read address of the last 50-TP
programmed memory location.
0
1
X
D2
D1
D0
Write contents of the serial
register data to the control
register.
8
1
0
X
Read contents of the control
register.
9
1
0
1
X
D0
Software shutdown.
D0 = 0; normal mode.
D0 = 1; shutdown mode.
1
X = don’t care.
2
AD5274 = don’t care.
3
See Table 16 for the 50-TP memory map.
4
See Table 15 for bit details.
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