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参数资料
| 型号： | AD5300 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Rail-to-Rail Voltage Output 8-Bit DAC(满幅度电压输出8位D/A转换器) |
| 中文描述： | 轨至轨电压输出的8位DAC（满幅度电压输出8位的D / A转换器） |
| 文件页数： | 10/12页 |
| 文件大小： | 221K |
| 代理商： | AD5300 |
AD5300
–10–
REV. 0
AD5300 to 68HC11/68L11 Interface
Figure 26 shows a serial interface between the AD5300 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the CLK IN of the AD5300, while the MOSI output
drives the serial data line of the DAC. T he
SYNC
signal is
derived from a port line (PC7). T he setup conditions for cor-
rect operation of this interface are as follows: the 68HC11/
68L11 should be configured so that its CPOL bit is a 0 and its
CPHA bit is a 1. When data is being transmitted to the DAC,
the
SYNC
line is taken low (PC7). When the 68HC11/68L11 is
configured as above, data appearing on the MOSI output is
valid on the falling edge of SCK . Serial data from the 68HC11/
68L11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
first. In order to load data to the AD5300, PC7 is left low after
the first eight bits are transferred, and a second serial write
operation is performed to the DAC and PC7 is taken high at the
end of this procedure.
SCLK
68HC11/68L11*
SCK
*ADDITIONAL PINS OMITTED FOR CLARITY
DIN
MOSI
AD5300*
PC7
Figure 26. AD5300 to 68HC11/68L11 Interface
AD5300 to 80C51/80L51 Interface
Figure 27 shows a serial interface between the AD5300 and the
80C51/80L51 microcontroller. T he setup for the interface is as
follows: T X D of the 80C51/80L51 drives SCLK of the AD5300,
while RX D drives the serial data line of the part. T he
SYNC
signal is again derived from a bit programmable pin on the port.
In this case port line P3.3 is used. When data is to be transmit-
ted to the AD5300, P3.3 is taken low. T he 80C51/80L51 trans-
mits data only in 8-bit bytes; thus only eight falling clock edges
occur in the transmit cycle. T o load data to the DAC, P3.3 is
left low after the first eight bits are transmitted, and a second
write cycle is initiated to transmit the second byte of data. P3.3
is taken high following the completion of this cycle. T he 80C51/
80L51 outputs the serial data in a format which has the LSB
first. T he AD5300 requires its data with the MSB as the first bit
received. T he 80C51/80L51 transmit routine should take this
into account.
SCLK
80C51/80L51*
TXD
*ADDITIONAL PINS OMITTED FOR CLARITY
DIN
RXD
AD5300*
P3.3
Figure 27. AD5300 to 80C51/80L51 Interface
AD5300 to Microwire Interface
Figure 28 shows an interface between the AD5300 and any
microwire compatible device. Serial data is shifted out on the
falling edge of the serial clock and is clocked into the AD5300
on the rising edge of the SK .
SCLK
MICROWIRE*
SK
*ADDITIONAL PINS OMITTED FOR CLARITY
DIN
SO
AD5300*
CS
Figure 28. AD5300 to Microwire Interface
APPLICAT IONS
Using RE F19x as a Power Supply for AD5300
Because the supply current required by the AD5300 is extremely
low, you have an alternative option is to use a REF19x voltage
reference (REF195 for 5 V or REF193 for 3 V) to supply the
required voltage to the part—see Figure 29. T his is especially
useful if your power supply is quite noisy or if the system supply
voltages are at some value other than 5 V or 3 V (e.g. 15 V).
T he REF19x will output a steady supply voltage for the AD5300.
If the low dropout REF195 is used, the current it needs to sup-
ply to the AD5300 is 140
μ
A. T his is with no load on the output
of the DAC. When the DAC output is loaded, the REF195 also
needs to supply the current to the load. T he total current re-
quired (with a 5 k
load on the DAC output) is:
140
μ
A
+ (5
V
/5
k
) = 1.14
mA
T he load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 2.3 ppm (11.5
μ
V) for the 1.14 mA
current drawn from it. T his corresponds to a 0.0006 LSB error.
3-WIRE
SERIAL
INTERFACE
SYNC
SCLK
DIN
+15V
+5V
140
m
A
V
OUT
= 0 to 5V
AD5300
REF195
Figure 29. REF195 as Power Supply to AD5300
Bipolar Operation Using the AD5300
T he AD5300 has been designed for single-supply operation, but
a bipolar output range is also possible using the circuit in Figure
30. T he circuit below will give an output voltage range of
±
5 V.
Rail-to-rail operation at the amplifier output is achievable using
an AD820 or an OP295 as the output amplifier.
T he output voltage for any input code can be calculated as
follows:
V
O
=
V
DD
×
D
256
×
R
1
+
R
2
R
1
±
V
DD
×
R
2
R
1
where
D
represents the input code in decimal (0–255).
With
V
DD
= 5 V,
R
1 =
R
2 = 10 k
:
V
O
=
10
×
D
256
±5
V
T his is an output voltage range of
±
5 V with 00 Hex corresponding
to a –5 V output and FF Hex corresponding to a +5 V output.
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