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参数资料
| 型号： | AD5300 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Rail-to-Rail Voltage Output 8-Bit DAC(满幅度电压输出8位D/A转换器) |
| 中文描述： | 轨至轨电压输出的8位DAC（满幅度电压输出8位的D / A转换器） |
| 文件页数： | 8/12页 |
| 文件大小： | 221K |
| 代理商： | AD5300 |
AD5300
–8–
REV. 0
GE NE RAL DE SCRIPT ION
D/A Section
T he AD5300 DAC is fabricated on a CMOS process. T he
architecture consists of a string DAC followed by an output
buffer amplifier. Since there is no reference input pin, the
power supply (V
DD
) acts as the reference. Figure 20 shows a
block diagram of the DAC architecture.
V
DD
V
OUT
GND
RESISTOR
STRING
REF (+)
REF (–)
OUTPUT
AMPLIFIER
DAC REGISTER
Figure 20. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by:
V
OUT
=
V
DD
×
D
256
where
D
= decimal equivalent of the binary code that is loaded
to the DAC register; it can range from 0 to 255.
R
R
R
R
R
TO OUTPUT
AMPLIFIER
Figure 21. Resistor String
Resistor String
T he resistor string section is shown in Figure 21. It is simply a
string of resistors, each of value R. T he code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. T he voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaran-
teed monotonic.
Output Amplifier
T he output buffer amplifier is capable of generating rail-to-rail
voltages on its output which gives an output range of 0 V to
V
DD
. It is capable of driving a load of 2 k
in parallel with
200 pF to GND. T he source and sink capabilities of the output
amplifier can be seen in Figures 8 and 9. T he slew rate is 1V/
μ
s
with a half-scale settling time of 4
μ
s with the output loaded.
SE RIAL INT E RFACE
T he AD5300 has a three-wire serial interface (
SYNC
, SCLK
and DIN), which is compatible with SPI, QSPI and Microwire
interface standards as well as most DSPs. See Figure 1 for a
timing diagram of a typical write sequence.
T he write sequence begins by bringing the
SYNC
line low. Data
from the DIN line is clocked into the 16-bit shift register on the
falling edge of SCLK . T he serial clock frequency can be as high
as 30 MHz, making the AD5300 compatible with high-speed
DSPs. On the sixteenth falling clock edge, the last data bit is
clocked in and the programmed function is executed (i.e. a
change in DAC register contents and/or a change in the mode of
operation). At this stage, the
SYNC
line may be kept low or be
brought high. In either case, it must be brought high for a mini-
mum of 33 ns before the next write sequence so that a falling
edge of
SYNC
can initiate the next write sequence. Since the
SYNC
buffer draws more current when V
IN
= 2.4 V than it does
when V
IN
= 0.8 V,
SYNC
should be idled low between write
sequences for even lower power operation of the part. As is
mentioned above, however, it must be brought high again just
before the next write sequence.
Input Shift Register
T he input shift register is 16 bits wide (see Figure 22). T he first
two bits are “don’t cares.” T he next two are control bits that
control which mode of operation the part is in (normal mode or
any one of three power-down modes). T here is a more complete
description of the various modes in the Power-Down Modes
section. T he next eight bits are the data bits. T hese are trans-
ferred to the DAC register on the sixteenth falling edge of SCLK.
Finally, the last four bits are “don’t cares.”
DB0 (LSB)
DB15 (MSB)
0
0
NORMAL OPERATION
0
1
1k
V
TO GND
1
1
0
1
100k
V
TO GND
THREE-STATE
DATA BITS
X
X
PD1
PD0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
POWER-DOWN MODES
Figure 22. Input Register Contents
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| AD53000-2 | 制造商:Analog Devices 功能描述:53000-2 |
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