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参数资料
| 型号： | AD5318 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP |
| 中文描述： | 2.5 V至5.5 V电压输出8-/10-/12-Bit八路数模转换器的16引脚TSSOP |
| 文件页数： | 12/19页 |
| 文件大小： | 308K |
| 代理商： | AD5318 |
REV. B
–12–
AD5308/AD5318/AD5328
SERIAL INTERFACE
The AD5308/AD5318/AD5328 are controlled over a versatile
3-wire serial interface that operates at clock rates up to 30 MHz
and is compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCLK. The timing diagram for this operation is shown in Figure 1.
The
SYNC
input is a level-triggered input that acts as a frame
synchronization signal and chip enable. Data can be transferred
into the device only while
SYNC
is low. To start the serial
data transfer,
SYNC
should be taken low, observing the mini-
mum
SYNC
to SCLK falling edge setup time, t
4.
After
SYNC
goes low, serial data will be shifted into the device’s input shift
register on the falling edges of SCLK for 16 clock pulses.
To end the transfer,
SYNC
must be taken high after the falling
edge of the 16th SCLK pulse, observing the minimum SCLK
falling edge to
SYNC
rising edge time, t
7
.
After the end of serial data transfer, data will automatically be
transferred from the input shift register to the input register of
the selected DAC. If
SYNC
is taken high before the 16th falling
edge of SCLK, the data transfer will be aborted and the DAC
input registers will not be updated.
Data is loaded MSB first (Bit 15). The first bit determines whether
it is a DAC write or a control function.
DAC Write
Here, the 16-bit word consists of one control bit and three
address bits followed by 8, 10, or 12 bits of DAC data, depending
on the device type. In the case of a DAC write, the MSB will be
a 0. The next three address bits determine whether the data is
for DAC A, DAC B, DAC C, DAC D, DAC E, DAC F, DAC
G, or DAC H. The AD5328 uses all 12 bits of DAC data. The
AD5318 uses 10 bits and ignores the two LSBs. The AD5308
uses eight bits and ignores the last four bits. These ignored
LSBs should be set to 0. The data format is straight binary,
with all 0s corresponding to 0 V output and all 1s corresponding
to full-scale output.
Table I. Address Bits for the AD53x8
A2 (Bit 14)
A1 (Bit 13)
A0 (Bit 12)
DAC Addressed
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
Control Functions
In the case of a control function, the MSB (Bit 15) will be a 1.
This is followed by two control bits, which determine the mode.
There are four different control modes, each of which is described
below. The write sequences for these modes are shown in Table II.
Reference and Gain Mode
This mode determines whether the reference for each group of
DACs is buffered, unbuffered, or from V
DD
. It also determines
the gain of the output amplifier. To set up the reference of both
groups, set the control bits to (00), set the GAIN bits, set the
BUF bits, and set the V
DD
bits.
BUF
Controls whether the reference of a group of DACs is
buffered or unbuffered. The reference of the first group of
DACs (A, B, C, and D) is controlled by setting Bit 2, and
the second group of DACs (E, F, G, and H) is con-
trolled by setting Bit 3.
0: Unbuffered reference.
1: Buffered reference.
GAIN
The gain of the DACs is controlled by setting Bit 4 for
the first group of DACs (A, B, C, and D) and Bit 5 for
the second group of DACs (E, F, G, and H).
0: Output range of 0 V to V
REF
.
1: Output range of 0 V to 2 V
REF
.
D
/C
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
BIT 0
(LSB)
BIT 15
(MSB)
DATA BITS
A1
A2
Figure 6. AD5308 Input Shift Register Contents
DATA BITS
A0
0
0
BIT 0
(LSB)
BIT 15
(MSB)
A1
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A2
D
/C
Figure 7. AD5318 Input Shift Register Contents
DATA BITS
D
/C
A0
BIT 0
(LSB)
BIT 15
(MSB)
A1
A2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D10
D11
Figure 8. AD5328 Input Shift Register Contents
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