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参数资料
| 型号： | AD5318 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP |
| 中文描述： | 2.5 V至5.5 V电压输出8-/10-/12-Bit八路数模转换器的16引脚TSSOP |
| 文件页数： | 13/19页 |
| 文件大小： | 308K |
| 代理商： | AD5318 |
REV. B
AD5308/AD5318/AD5328
–13–
V
DD
These bits are set when V
DD
is to be used as reference.
The first group of DACs (A, B, C, and D) can be set
up to use V
DD
by setting Bit 0, and the second group of
DACs (E, F, G, and H) by setting Bit 1. The V
DD
bits
have priority over the BUF bits.
When V
DD
is used as the reference, it will always be
unbuffered and with an output range of 0 V to V
REF
,
regardless of the state of the GAIN and BUF bits.
LDAC
Mode
LDAC
mode controls
LDAC
, which determines when data is
transferred from the input registers to the DAC registers. There
are three options when updating the DAC registers, as shown in
Table III.
Table III.
LDAC
Mode
Bit
15
Bit
14
Bit
13
Bits
12 .... 2
Bit
1
Bit
0
Description
1
1
1
1
0
0
0
0
1
1
1
1
x ..... x
x ..... x
x ..... x
x ..... x
0
0
1
1
0
1
0
1
LDAC
Low
LDAC
High
LDAC
Single Update
Reserved
LDAC
Low (00)
:
This option sets
LDAC
permanently low,
allowing the DAC registers to be updated continuously.
LDAC
High (01):
This option sets
LDAC
permanently high.
The DAC registers are latched, and the input registers may
change without affecting the contents of the DAC registers.
This is the default option for this mode.
LDAC
Single Update (10):
This option causes a single pulse on
LDAC
, updating the DAC registers once.
Reserved (11):
Reserved.
Power-Down Mode
The individual channels of the AD5308/AD5318/AD5328 can
be powered down separately. The control mode for this is (10).
On completion of this write sequence, the channels that have
been set to 1 are powered down.
Table II. Control Words for the AD53x8
D
/C
15
Control Bits
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Mode
(
GAIN Bits
)
E..H
(
BUF Bits
)
E..H
(
V
DD
Bits
)
E..H
Gain of Output Amplifier
and Reference Selection
1
0
0
x
x
x
x
x
x
x
A..D
A..D
A..D
(
LDAC
Bits
)
1/0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
1/0
LDAC
(
Channels
)
G
F
1
1
0
x
x
x
x
x
H
E
D
C
B
A
Power-Down
(
RESET
)
1
1
1
1/0
x
x
x
x
x
x
x
x
x
x
x
x
Reset
Reset Mode
This mode consists of two possible reset functions, as outlined
in Table IV.
Table IV. Reset Mode
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11 .... 0
Description
1
1
1
1
1
1
0
1
x .... x
x .... x
DAC Data Reset
Data and Control Reset
DAC Data Reset:
On completion of this write sequence, all
DAC registers and input registers are filled with 0s.
Data and Control Reset:
This function carries out a DAC data
reset and also resets all the control bits (GAIN, BUF, V
DD
,
LDAC
, and power-down channels) to their power-on conditions.
Low Power Serial Interface
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, i.e., on
the falling edge of
SYNC
. The SCLK and DIN input buffers
are powered down on the rising edge of
SYNC
.
LOAD DAC INPUT (
LDAC
) FUNCTION
Access to the DAC registers is controlled by both the
LDAC
pin and the
LDAC
mode bits. The operation of the
LDAC
function can be likened to the configuration shown in Figure 9.
EXTERNAL
LDAC
PIN
INTERNAL
LDAC
MODE
LDAC
FUNCTION
Figure 9.
LDAC
Function
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