参数资料
型号: AD5320
厂商: Analog Devices, Inc.
英文描述: +2.7 V to +5.5 V, 140 uA, Rail-to-Rail Output 12-Bit DAC in a SOT-23
中文描述: 2.7 V至5.5 V,140微安,轨到轨输出12位DAC采用SOT - 23
文件页数: 11/12页
文件大小: 192K
代理商: AD5320
AD5320
–11–
REV. B
Bipolar Operation Using the AD5320
The AD5320 has been designed for single-supply operation but
a bipolar output range is also possible using the circuit in Figure
30. The circuit below will give an output voltage range of
±
5 V.
Rail-to-rail operation at the amplifier output is achievable using
an AD820 or an OP295 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
V
O
=
V
DD
×
D
4096
×
R
1
+
R
2
R
1
V
DD
×
R
2
R
1
where
D
represents the input code in decimal (0–4095).
With
V
DD
= 5 V,
R
1 =
R
2 = 10 k
:
V
O
=
10
×
D
4096
–5
V
This is an output voltage range of
±
5 V with 000 Hex corre-
sponding to a –5 V output and FFF Hex corresponding to a
+5 V output.
THREE-WIRE
SERIAL
INTERFACE
+5V
AD5320
10 F
0.1 F
V
DD
V
OUT
R1 = 10k
R2 = 10k
+5V
5V
5V
AD820/
OP295
Figure 30. Bipolar Operation with the AD5320
Using AD5320 with an Opto-Isolated Interface
In process-control applications in industrial environments it is
often necessary to use an opto-isolated interface to protect and
isolate the controlling circuitry from any hazardous common-
mode voltages that may occur in the area where the DAC is
functioning. Opto-isolators provide isolation in excess of 3 kV.
Because the AD5320 uses a three-wire serial logic interface, it
requires only three opto-isolators to provide the required isola-
tion (see Figure 31). The power supply to the part also needs to
be isolated. This is done by using a transformer. On the DAC
side of the transformer, a +5 V regulator provides the +5 V
supply required for the AD5320.
V
DD
0.1 F
V
DD
10k
10k
V
DD
10k
+5V
REGULATOR
V
OUT
GND
DIN
SYNC
SCLK
POWER
10 F
V
DD
SYNC
SCLK
DATA
AD5320
Figure 31. AD5320 with An Opto-Isolated Interface
Power Supply Bypassing and Grounding
When accuracy is important in a circuit it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5320 should
have separate analog and digital sections, each having its own
area of the board. If the AD5320 is in a system where other
devices require an AGND to DGND connection, the connec-
tion should be made at one point only. This ground point
should be as close as possible to the AD5320.
The power supply to the AD5320 should be bypassed with
10
μ
F and 0.1
μ
F capacitors. The capacitors should be physi-
cally as close as possible to the device with the 0.1
μ
F capacitor
ideally right up against the device. The 10
μ
F capacitors are the
tantalum bead type. It is important that the 0.1
μ
F capacitor has
low Effective Series Resistance (ESR) and Effective Series In-
ductance (ESI), e.g., common ceramic types of capacitors. This
0.1
μ
F capacitor provides a low impedance path to ground for
high frequencies caused by transient currents due to internal
logic switching.
The power supply line itself should have as large a trace as pos-
sible to provide a low impedance path and reduce glitch effects
on the supply line. Clocks and other fast switching digital signals
should be shielded from other parts of the board by digital
ground. Avoid crossover of digital and analog signals if possible.
When traces cross on opposite sides of the board, ensure that
they run at right angles to each other to reduce feedthrough
effects through the board. The best board layout technique is
the microstrip technique where the component side of the board
is dedicated to the ground plane only and the signal traces are
placed on the solder side. However, this is not always possible
with a two-layer board.
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