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参数资料
| 型号： | AD53500JRP |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 外设及接口 |
| 英文描述： | High Speed, High Current Capability Pin Driver |
| 中文描述： | 0.4 A BUF OR INV BASED PRPHL DRVR, PDSO20 |
| 封装： | POWER, SOIC-20 |
| 文件页数： | 5/7页 |
| 文件大小： | 101K |
| 代理商： | AD53500JRP |
AD53500
–5–
REV. 0
capacitor to the positive supply (and the V
LDCPL
capacitor to the
negative supply)—failure to do so causes considerable thermal
stress in the current-limiting resistor(s) during normal supply
sequencing and may ultimately cause them to fail, rendering the
part nonfunctional. Finally, the AD53500 may appear to func-
tion normally for small output steps (less than 3 V or so) if one
or both of these caps is absent, but it may exhibit excessive rise
or fall times for steps of larger amplitude.
The AD53500 does not require special power-supply sequenc-
ing. However, good design practice dictates that digital and
analog control signals not be applied to the part before the sup-
plies are stable. Violating this guideline will not normally de-
stroy the part, but the active inputs can draw considerable
current until the main supplies are applied.
RISING-EDGE SLEW
CONTROL CURRENT
5
V
V+
V
HDCPL
LEVEL-SHIFTED
LOGIC DRIVE
V
H
V–
Q49
OUT
Q50
Q48
Figure 2. Simplified Schematic of the AD53500 Output
Stage and Positive Current-Limit Circuitry
APPLICATION INFORMATION
Power Supply Distribution, Bypassing and Sequencing
The AD53500 draws substantial transient currents from its
power supplies when switching between states and careful de-
sign of the power distribution and bypassing is key to obtaining
specified performance. Supplies should be distributed using
broad, low inductance traces or (preferably) planes in a multi-
layered board with a dedicated ground-plane layer. All of the
device’s power supply pins should be used to minimize the inter-
nal inductance presented by the part’s bond wires. Each supply
must be bypassed to ground with at least one 0.1
μ
F capacitor;
chip-style capacitors are preferable as they minimize inductance.
One or more 10
μ
F (or greater) Tantalum capacitors per board
are also advisable to provide additional local energy storage.
The AD53500’s current-limit circuitry also requires external
bypass capacitors. Figure 2 shows a simplified schematic of the
positive current-limit circuit. Excessive collector current in
output transistor Q49 creates a voltage drop across the 5
resistor, which turns on PNP transistor Q48. Q48 diverts the
rising-edge slew current, shutting down the current mirror and
removing the output stage’s base drive. The V
HDCPL
pin should
be bypassed to the positive supply with a 0.039
F capacitor,
while the V
LDCPL
pin (not shown) requires a similar capacitor to
the negative supply. These capacitors ensure that the AD53500
does not current-limit during normal output transitions up its
full 8 V rated step size. Both capacitors must have minimum-
length connections to the AD53500. Here again, chip capacitors
are ideal.
Several points about the current-limit circuitry should be noted.
First, the limiting currents are not tightly controlled, as they are
functions of both absolute transistor V
BE
and junction tempera-
ture; higher dc output current is available at lower junction
temperatures. Second, it is essential to connect the V
HDCPL
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