参数资料
型号: AD5382BST-5
厂商: ANALOG DEVICES INC
元件分类: DAC
英文描述: 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC
中文描述: PARALLEL, WORD INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP100
封装: 14 X 14 MM, MS-026BED, LQFP-100
文件页数: 8/40页
文件大小: 616K
代理商: AD5382BST-5
AD5382
TIMING CHARACTERISTICS
SPI, QSPI, MICROWIRE, OR DSP COMPATIBLE SERIAL INTERFACE
Table 6. DV
DD
= 2.7 V to 5.5 V ; AV
DD
= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications
T
MIN
to T
MAX
, unless otherwise noted
Parameter
1
,
2
,
3
Limit at T
MIN
, T
MAX
Unit
t
1
33
ns min
t
2
13
ns min
t
3
13
ns min
t
4
13
ns min
t
5
4
13
ns min
t
6
4
33
ns min
t
7
10
ns min
t
7A
50
ns min
t
8
5
ns min
t
9
4.5
ns min
t
104
30
ns max
t
11
670
ns max
t
12 4
20
ns min
t
13
20
ns min
t
14
100
ns max
t
15
0
ns min
t
16
100
ns min
t
17
8
μs typ
t
18
20
ns min
t
19
35
μs max
t
20
5
20
ns max
t
215
5
ns min
t
225
8
ns min
t
23
20
ns min
Rev. 0 | Page 8 of 40
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th SCLK falling edge to SYNC falling edge
Minimum SYNC low time
Minimum SYNC high time
Minimum SYNC high time in Readback mode
Data setup time
Data hold time
24th SCLK falling edge to BUSY falling edge
BUSY pulse width low (single channel update)
24th SCLK falling edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of V
CC
) and are timed from a voltage level of 1.2 V.
3
See Figure 2, Figure 3, Figure 4, and Figure 5.
4
Standalone mode only.
5
Daisy-chain mode only.
C
50pF
TO OUTPUT PIN
V
OH
(MIN) OR
V
OL
(MAX)
200
μ
A
200
μ
A
I
OL
I
OH
0
Figure 2. Load Circuit for SDO Timing Diagram
(Serial Interface, Daisy-Chain Mode)
相关PDF资料
PDF描述
AD5382BST-5-REEL 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC
AD5383BST-3 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC
AD5383BST-5 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC
AD5383 32-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC
AD5383BST-3-REEL 32-Channel, 3 V/5 V, Single-Supply, 12-Bit, Voltage Output DAC
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