参数资料
型号: AD5382BSTZ-3
厂商: Analog Devices Inc
文件页数: 25/40页
文件大小: 0K
描述: IC DAC 14BIT 32CHAN 3V 100LQFP
产品培训模块: Data Converter Fundamentals
DAC Architectures
产品变化通告: Redesign Change 28/Oct/2011
设计资源: 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5382 (CN0011)
AD5382 Channel Monitor Function (CN0012)
标准包装: 1
设置时间: 8µs
位数: 14
数据接口: 串行,并联
转换器数目: 32
电压电源: 单电源
功率耗散(最大): 65mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 托盘
输出数目和类型: 32 电压,单极
采样率(每秒): 125k
Data Sheet
AD5382
Rev. C | Page 31 of 40
MICROPROCESSOR INTERFACING
Parallel Interface
The AD5382 can be interfaced to a variety of 16-bit microcon-
trollers or DSP processors. Figure 34 shows the AD5382 family
interfaced to a generic 16-bit microcontroller/DSP processor.
The lower address lines from the processor are connected to
A0–A4 on the AD5382. The upper address lines are decoded
to provide a CS, LDAC signal for the AD5382. The fast interface
timing of the AD5382 allows direct interface to a wide variety
of microcontrollers and DSPs, as shown in Figure 34.
AD5382 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR = 1), Clock Polarity bit
(CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the
SCLK of the AD5382, the MOSI output drives the serial data
line (DIN) of the AD5382, and the MISO input is driven from
DOUT. The SYNC signal is derived from a port line (PC7).
When data is being transmitted to the AD5382, the SYNC line
is taken low (PC7). Data appearing on the MOSI output is valid
on the falling edge of SCK. Serial data from the 68HC11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle.
03733-034
MC68HC111
AD53821
MISO
MOSI
SCK
PC7
SDO
RESET
SER/PAR
DIN
SCLK
SYNC
SPI/I2C
DVDD
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 33. AD5382-to-MC68HC11 Interface
03733-035
CONTROLLER/
DSP PROCESSOR1
AD53821
ADDRESS
DECODE
UPPER BITS OF
ADDRESS BUS
DATA
BUS
D15
D0
A4
A3
A2
A1
A0
R/W
A4
A3
A2
A1
A0
WR
REG1
REG0
D13
D0
CS
LDAC
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 34. AD5382-to-Parallel Interface
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