参数资料
| 型号： | AD5383BSTZ-5 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/40页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT 32CH 5V 100-LQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 产品变化通告： | AD5381,3 Redesign Change 24/Oct/2011 |
| 设计资源： | 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5383 (CN0014) AD5383 Channel Monitor Function (CN0015) |
| 标准包装： | 1 |
| 设置时间： | 6µs |
| 位数： | 12 |
| 数据接口： | 串行，并联 |
| 转换器数目： | 32 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 65mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（14x14） |
| 包装： | 托盘 |
| 输出数目和类型： | 32 电压，单极；32 电压，双极 |
| 采样率（每秒）： | 167k |
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Data Sheet
AD5383
Rev. C | Page 27 of 40
Daisy-Chain Mode
For systems that contain several devices, the SDO pin may be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines.
By connecting the DCEN (daisy-chain enable) pin high, daisy-
chain mode is enabled. The first falling edge of SYNC starts the
write cycle. The SCLK is continuously applied to the input shift
register when SYNC is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting the SDO
of the first device to the DIN input on the next device in the
chain, a multidevice interface is constructed. Twenty-four clock
pulses are required for each device in the system. Therefore, the
total number of clock cycles must equal 24N, where N is the
total number of AD538x devices in the chain.
When the serial transfer to all devices is complete, SYNC is
taken high. This latches the input data in each device in the
daisy-chain and prevents any further data from being clocked
into the input shift register.
If SYNC is taken high before 24 clocks are clocked into the part,
this is considered a bad frame and the data is discarded.
The serial clock may be either a continuous or a gated clock. A
continuous SCLK source can only be used if SYNC can be held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used and SYNC must be taken high after the final clock to
latch the data.
Readback Mode
Readback mode is invoked by setting the R/W bit = 1 in the
serial input register write. With R/W = 1, Bits A4 to A0, in
association with Bits REG1 and REG0, select the register to be
read. The remaining data bits in the write sequence are don’t
cares. During the next SPI write, the data appearing on the SDO
output will contain the data from the previously addressed
register. For a read of a single register, the NOP command can
be used in clocking out the data from the selected register on
SDO. Figure 30 shows the readback sequence. For example, to
read back the m register of Channel 0 on the AD5383, the
following sequence should be implemented. First, write
0x404XXX to the AD5383 input register. This configures the
AD5383 for read mode with the m register of Channel 0
selected. Note that Data Bits DB11 to DB0 are don’t cares.
Follow this with a second write, a NOP condition, 0x000000.
During this write, the data from the m register is clocked out on
the DOUT line, that is, data clocked out will contain the data from
the m register in Bits DB11 to DB0, and the top 10 bits contain
the address information as previously written. In readback
mode, the SYNC signal must frame the data. Data is clocked out
on the rising edge of SCLK and is valid on the falling edge of
the SCLK signal. If the SCLK idles high between the write and
read operations of a readback operation, the first bit of data is
clocked out on the falling edge of SYNC.
03734-030
24
48
SCLK
SYNC
DIN
SDO
UNDEFINED
SELECTED REGISTER DATA CLOCKED OUT
NOP CONDITION
INPUT WORD SPECIFIES REGISTER TO BE READ
DB23
DB0
DB23
DB0
DB23
Figure 30. Serial Readback Operation
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