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| 型号： | AD5384BBCZ-3 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 22/32页 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 40CH 5V 100-CSPBGA |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 产品变化通告： | AD5384 Models Discontinuation 15/May/2012 |
| 标准包装： | 1 |
| 设置时间： | 8µs |
| 位数： | 14 |
| 数据接口： | 串行 |
| 转换器数目： | 40 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 80mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LFBGA，CSPBGA |
| 供应商设备封装： | 100-CSBGA（10x10） |
| 包装： | 托盘 |
| 输出数目和类型： | 40 电压，单极 |
| 采样率（每秒）： | 125k |
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Data Sheet
AD5384
APPLICATIONS INFORMATION
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of
the power supply and ground return layout helps to ensure the
rated performance. Separate and confine the analog and digital
sections to certain areas of the printed circuit board (PCB) of
the AD5384. If the AD5384 is in a system where multiple
devices require an AGND-to-DGND connection, make the
connection at one point only, a star ground point established as
near to the device as possible.
For supplies with multiple pins (AVDDx, and AVCCx), tie these
pins together. Allow ample supply bypassing of 10 F
capacitators in parallel with 0.1 F capacitors on each supply,
located as near the package as possible and ideally right up
against the AD5384 device. The 10 F capacitors are the
tantalum bead type. The 0.1 F capacitor has low effective series
resistance (ESR) and effective series inductance (ESI), such as
the common ceramic types that provide a low impedance path
to ground at high frequencies, so that it can handle transient
currents due to internal logic switching.
The power supply lines of the AD5384 use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Shield fast switching
signals, such as clocks, with digital ground to avoid radiating
noise elsewhere on the board, and do not run them near the
reference inputs. A ground line routed between the DIN and
SCLK lines helps to reduce crosstalk between them (this is not
required on a multilayer board because there is a separate
ground plane; however, separating the lines helps). It is essential
to minimize noise on the VIN and REF_IN lines.
Avoid crossover of digital and analog signals. Run the traces on
opposite sides of the board at right angles to each other. This
reduces the effects of feedthrough through the board. A
microstrip technique is by far the best; however, it is not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to the ground plane
while signal traces are placed on the solder side.
MONITOR FUNCTION
The AD5384 contains a channel monitor function that consists
of a multiplexer addressed via the interface, allowing any
channel output to be routed to this pin for monitoring, using an
external ADC. In channel monitor mode, VOUT39 becomes the
MON_OUT pin, to which all monitored signals are routed. Enable
the channel monitor function in the control register before any
channels are routed to the MON_OUT pin.
Table 14 shows the decoding information required to route any
channel to MON_OUT. Selecting Channel Address 63 three-states
the MON_OUT pin. Figure 30 shows a typical monitoring circuit
implemented using a 12-bit SAR ADC in a 6-lead SOT package.
The controller output port selects the channel to monitor, and the
input port reads the converted data from the ADC.
AD7476
GND
SDATA
CS
SCLK
AVCCx
VIN
VOUT39/MON_OUT
AGNDx
DIN/SDA
SYNC/AD0
SCLK/SCL
DAC_GND SIGNAL_GND
VOUT0
VOUT38
AVCCx
AD5384
OUTPUT PORT
INPUT PORT
CONTROLLER
04652-
032
Figure 30. Typical Channel Monitoring Circuit
TOGGLE MODE FUNCTION
The toggle mode function allows an output signal to be generated
using the LDAC control signal, which switches between two DAC
data registers. This function is configured using the SFR control
register as follows: A write with REG1 = REG0 = 0 and A5 to A0 =
001100 specifies a control register write. The toggle mode function
is enabled in groups of eight channels using Bit CR6 to Bit CR2 in
the control register (see Table 12). Figure 31 shows a block diagram
of toggle mode implementation.
14-BIT DAC
DAC
REGISTER
INPUT
DATA
INPUT
REGISTER
DATA
REGISTER
B
DATA
REGISTER
A
A/B
VOUT
LDAC
CONTROL INPUT
04652-
033
Figure 31. Toggle Mode Function
Rev. B | Page 29 of 32
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