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参数资料
| 型号： | AD5420AREZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/32页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT 1CH SER 24TSSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 设计资源： | Simplified 16-Bit, 4 mA-to-20 mA Output Solution Using AD5420 (CN0098) |
| 标准包装： | 1,000 |
| 设置时间： | 10µs |
| 位数： | 16 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 950mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 供应商设备封装： | 24-TSSOP 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 1 电流，单极 |
| 采样率（每秒）： | * |
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AD5410/AD5420
Data Sheet
Rev. F | Page 24 of 32
The time it takes for the output current to slew over a given
output range can be expressed as follows:
Size
LSB
Frequency
Clock
Update
Size
Step
Change
Output
Time
Slew
×
=
(1)
where:
Slew Time is expressed in seconds.
Output Change is expressed in amps.
When the slew rate control feature is enabled, all output
changes change at the programmed slew rate. If the CLEAR
pin is asserted, the output slews to the zero-scale value at the
programmed slew rate. The output can be halted at its current
value with a write to the control register. To avoid halting the
output slew, the slew active bit can be read to check that the
slew has completed before writing to any of the AD5410/
any given value is the same for all output ranges. The step size,
however, varies across output ranges for a given value of step
size because the LSB size is different for each output range.
Table 20 shows the range of programmable slew times for a full-
scale change on any of the output ranges. The values in Table 20
were obtained using Equation 1. The digital slew rate control
feature results in a staircase formation on the current output, as
shown in Figure 47. Figure 47 also shows how the staircase can
be removed by connecting capacitors to the CAP1 and CAP2
pins, as described in the IOUT Filtering Capacitors section.
Table 20. Programmable Slew Time Values in Seconds for a Full-Scale Change on Any Output Range
Step Size (LSBs)
Update Clock Frequency (Hz)
1
2
4
8
16
32
64
128
257,730
0.25
0.13
0.06
0.03
0.016
0.008
0.004
0.0020
198,410
0.33
0.17
0.08
0.04
0.021
0.010
0.005
0.0026
152,440
0.43
0.21
0.11
0.05
0.027
0.013
0.007
0.0034
131,580
0.50
0.25
0.12
0.06
0.031
0.016
0.008
0.0039
115,740
0.57
0.28
0.14
0.07
0.035
0.018
0.009
0.0044
69,440
0.9
0.47
0.24
0.12
0.06
0.03
0.015
0.007
37,590
1.7
0.87
0.44
0.22
0.11
0.05
0.03
0.014
25,770
2.5
1.3
0.64
0.32
0.16
0.08
0.04
0.020
20,160
3.3
1.6
0.81
0.41
0.20
0.10
0.05
0.025
16,030
4.1
2.0
1.0
0.51
0.26
0.13
0.06
0.03
10,290
6.4
3.2
1.6
0.80
0.40
0.20
0.10
0.05
8280
7.9
4.0
2.0
1.0
0.49
0.25
0.12
0.06
6900
9.5
4.8
2.4
1.2
0.59
0.30
0.15
0.07
5530
12
5.9
3.0
1.5
0.74
0.37
0.19
0.09
4240
15
7.7
3.9
1.9
0.97
0.48
0.24
0.12
3300
20
9.9
5.0
2.5
1.24
0.62
0.31
0.16
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