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参数资料
| 型号： | AD5424YRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/29页 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT MULTIPLYING 16-TSSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 2,500 |
| 设置时间： | 30ns |
| 位数： | 8 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 25µW |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电流，单极；2 电流，双极 |
| 采样率（每秒）： | 20.4M |
| 配用： | EVAL-AD5424EBZ-ND - BOARD EVALUATION FOR AD5424 |
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Data Sheet
AD5424/AD5433/AD5445
Rev. D | Page 19 of 28
03160-050
VREF
±10V
VDD
R/W
R2
R1
R3
20k
R4
10k
R5
20k
IOUT1
IOUT2
CS
RFB
GND
C1
A1
A2
AGND
DATA
INPUTS
VOUT = –VREF TO +VREF
AD5424/
AD5433/
AD5445
R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC.
MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.
C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS
A HIGH SPEED AMPLIFIER.
NOTES:
1.
2.
3.
VREF
Figure 50. Bipolar Operation (4-Quadrant Multiplication)
BIPOLAR OPERATION
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and some external resistors, as shown in Figure 50.
In this circuit, the second amplifier, A2, provides a gain of 2.
Biasing the external amplifier with an offset from the reference
voltage, results in full 4-quadrant multiplying operation. The
transfer function of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from code zero (VOUT = –VREF) to midscale
(VOUT = 0 V) to full scale (VOUT = +VREF).
(
)
REF
n
REF
OUT
V
D
V
×
=
1
2
/
where D is the fractional representation of the digital word
loaded to the DAC and n is the resolution of the DAC.
D = 0 to 255 (8-bit AD5424)
= 0 to 1023 (10-bit AD5433)
= 0 to 4095 (12-bit AD5445)
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication.
Table 8 shows the relationship between digital code and the
expected output voltage for bipolar operation (AD5424,
8-bit device).
Table 8. Bipolar Code Table
Digital Input
Analog Output (V)
1111 1111
+VREF (127/128)
1000 0000
0
0000 0001
–VREF (127/128)
0000 0000
–VREF (128/128)
Stability
In the I-to-V configuration, the IOUT of the DAC and the inverting
node of the op amp must be connected as closely as possible and
proper PCB layout techniques must be employed. Since every code
change corresponds to a step function, gain peaking may occur
if the op amp has limited GBP and there is excessive parasitic
capacitance at the inverting node. This parasitic capacitance
introduces a pole into the open-loop response, which can cause
ringing or instability in closed-loop applications.
An optional compensation capacitor, C1, can be added in parallel
small a value of C1 can produce ringing at the output, while too
large a value can adversely affect the settling time. C1 should be
found empirically, but 1 pF to 2 pF is generally adequate for
compensation.
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