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| 型号： | AD5700ACPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/24页 |
| 文件大小： | 0K |
| 描述： | IC HART MODEM LP 24LFCSP |
| 标准包装： | 1,500 |
| 系列： | * |
AD5700/AD5700-1
Data Sheet
Rev. F | Page 12 of 24
TERMINOLOGY
VCC and IOVCC Current Consumption
This specification gives a summation of the current consump-
separate measurements for VCC and IOVCC currents vs. varying
capacitive loads, in transmit mode.
Load Regulation
Load regulation is the change in reference output voltage due to
a specified change in load current. It is expressed in ppm/A.
CD Assert
The minimum value at which the carrier detect signal asserts is
85 mV p-p and the maximum value it asserts at is 110 mV p-p. CD
is already high (asserted) for HART input signals greater than
110 mV p-p. This specification was set assuming a sinusoidal
input signal containing preamble characters at the input and an
ideal external filter (see Figure 23).
HART_OUT Output Voltage
This is the peak-to-peak HART_OUT output voltage. The
specification in Table 2 was set using a worst-case load of 160 ,
ac-coupled with a 2.2 F capacitor. Figure 17 and Figure 18 show
HART_OUT output voltages for both resistive and purely
capacitive loads.
Mark/Space Frequency
A 1.2 kHz signal represents a digital 1, or mark, whereas a
2.2 kHz signal represents a 0, or space.
Phase Continuity Error
The DDS engine in this design inherently generates continuous
phase signals, thus avoiding any output discontinuity when
switching between frequencies. This attribute is desirable for
signals that are to be transmitted over a band limited channel,
because discontinuities in a signal introduce wideband fre-
quency components. As the name suggests, for a signal to be
continuous, the phase continuity error must be 0o.
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