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| 型号： | AD5700ACPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/24页 |
| 文件大小： | 0K |
| 描述： | IC HART MODEM LP 24LFCSP |
| 标准包装： | 1,500 |
| 系列： | * |
Data Sheet
AD5700/AD5700-1
Rev. F | Page 13 of 24
THEORY OF OPERATION
Highway Addressable Remote Transducer (HART) Communica-
tion is the global standard for sending and receiving digital
information across analog wires between smart field devices
and control systems. This is a digital two-way communication
system, in which a 1 mA p-p frequency shift keyed (FSK) signal
is modulated on top of a 4 mA to 20 mA analog current signal.
The AD5700/AD5700-1 are designed and specified to operate
as a single-chip, low power, HART FSK half-duplex modem,
complying with the HART physical layer requirements
(Revision 8.1).
A single-chip solution, the AD5700/AD5700-1 not only inte-
grate the modulation and demodulation functions, but also
contain an internal reference, an integrated receive band-pass
filter (which has the flexibility of being bypassed if required),
and an internally buffered HART output, giving a high output
drive capability and removing the need for external buffering.
The AD5700-1 option also contains a precision internal RC
oscillator. The block diagram in Figure 1 shows a graphical
illustration of how these circuit blocks are connected together.
As a result of such extensive integration options, minimal
are suitable for use in both HART field instrument and master
configurations.
The AD5700/AD5700-1 either transmit or receive 1.2 kHz and
2.2 kHz carrier signals. A 1.2 kHz signal represents a digital 1,
or mark, whereas a 2.2 kHz signal represents a 0, or space.
There are three main clocking configurations supported by
these parts, two of which are available on the AD5700 option,
whereas all three are available on the AD5700-1 device:
External crystal
CMOS clock input
Internal RC oscillator (AD5700-1 only)
The device is controlled via a standard UART interface. The
relevant signals are RTS, CD, TXD, and RXD (see Table 6 for
more detail on individual pin descriptions).
FSK MODULATOR
The modulator converts a bit stream of UART-encoded HART
data at the TXD input to a sequence of 1200 Hz and 2200 Hz
tones (see Figure 19). This sinusoidal signal is internally buff-
ered and output on the HART_OUT pin. The modulator is
enabled by bringing the RTS signal low.
Figure 19. AD5700/AD5700-1 Modulator Waveform
The modulator block contains a DDS engine that produces a
1.2 kHz or 2.2 kHz sine wave in digital form and then performs
a digital-to-analog conversion. This DDS engine inherently
generates continuous phase signals, thus avoiding any output
discontinuity when switching between frequencies. For more
information on DDS fundamentals, see MT-085, Fundamentals
of Direct Digital Synthesizers (DDS). Figure 20 demonstrates a
simple implementation of this FSK encoding.
Figure 20. DDS-Based FSK Encoder
10435-
016
STOP
START
8-BIT DATA + PARITY
TXD
HART_OUT
"1" = MARK
1.2kHz
"0" = SPACE
2.2kHz
10435-
017
1.2kHz
WORD
2.2kHz
WORD
MU
X
DDS
DAC
FSK
0
DATA
1
CLOCK
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| AD57050/+ | 制造商:Analog Devices 功能描述: |
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