- 您现在的位置：买卖IC网 > PDF目录1979 > AD5763CSUZ-REEL7 (Analog Devices Inc)DAC 16BIT DUAL 5V 2LSB 32-TQFP PDF资料下载
参数资料
| 型号： | AD5763CSUZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/28页 |
| 文件大小： | 0K |
| 描述： | DAC 16BIT DUAL 5V 2LSB 32-TQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 产品变化通告： | AD5763/65 Metal Layer Edit Change 08/Sept/2009 |
| 设计资源： | High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5763 (CN0074) |
| 标准包装： | 500 |
| 设置时间： | 8µs |
| 位数： | 16 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 双 ± |
| 功率耗散（最大）： | 45mW |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电压，双极 |
| 采样率（每秒）： | * |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
AD5763
Data Sheet
Rev. C | Page 16 of 28
THEORY OF OPERATION
The AD5763 is a dual, 16-bit, serial input, bipolar voltage
output DAC and operates from supply voltages of ±4.75 V to
±5.25 V. The part has a specified buffered output voltage of up
to ±4.311 V. Data is written to the AD5763 in a 24-bit word
format via a 3-wire serial interface. The device also offers an
SDO pin, which is available for daisy-chaining or readback.
The AD5763 incorporates a power-on reset circuit, which
ensures that the DAC registers power-up loaded with 0x0000.
The AD5763 features a digital I/O port that can be programmed
via the serial interface, on-chip reference buffers, per channel
digital gain, and offset registers.
DAC ARCHITECTURE
The DAC architecture of the AD5763 consists of a 16-bit
current mode segmented R-2R ladder DAC. The simplified
circuit diagram for the DAC section is shown in Figure 25.
The four MSBs of the 16-bit data-word are decoded to drive
15 switches, E1 to E15. Each of these switches connects one
of the 15 matched resistors to either AGNDx or IOUT. The
remaining 12 bits of the data-word drive Switch S0 to Switch
S11 of the 12-bit R-2R ladder network.
2R
E15
VREF
2R
E14
E1
2R
S11
RR
R
2R
S10
2R
12-BIT, R-2R LADDER
4 MSBs DECODED INTO
15 EQUAL SEGMENTS
VOUTx
2R
S0
2R
AGNDx
R/8
IOUT
07
250
-03
1
Figure 25. DAC Ladder Structure
REFERENCE BUFFERS
The AD5763 operates with an external reference. The reference
inputs (REFA and REFB) have an input range up to 2.1 V. This
input voltage is then used to provide a buffered positive and
negative reference for the DAC cores. The positive reference
(VREFP) is given by
VREFP = 2VREF
The negative reference (VREFN) to the DAC cores is given by
VREFN = 2VREF
These positive and negative reference voltages (along with the
gain register values) define the output ranges of the DACs.
SERIAL INTERFACE
The AD5763 is controlled over a versatile 3-wire serial interface
that operates at clock rates of up to 30 MHz and is compatible
with SPI, QSPI, MICROWIRE, and DSP standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. The input register consists of a read/write
bit, three register select bits, three DAC address bits and 16
data bits as shown in Table 8. The timing diagram for this
operation is shown in Figure 2.
Upon power-up, the DAC registers are loaded with zero code
(0x0000) and the outputs are clamped to 0 V via a low impedance
path. The outputs can be updated with the zero code value at this
time by asserting either LDAC or CLR. The corresponding output
voltage depends on the state of the BIN/2sCOMP pin. If BIN/
2sCOMP is tied to DGND, then the data coding is twos comple-
ment and the outputs update to 0 V. If the BIN/2sCOMP pin is
tied to DVCC, then the data coding is offset binary and the outputs
update to negative full-scale. To have the outputs power-up with
zero code loaded to the outputs, the CLR pin should be held low
during power-up.
Standalone Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can only be
used if SYNC is held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used and SYNC must be taken high after
the final clock to latch the data. The first falling edge of SYNC
starts the write cycle. Exactly 24 falling clock edges must be
applied to SCLK before SYNC is brought high again. If SYNC is
brought high before the 24th falling SCLK edge, then the data
written is invalid. If more than 24 falling SCLK edges are
applied before SYNC is brought high, then the input data
is also invalid. The addressed input register is updated on the
rising edge of SYNC. For another serial transfer to take place,
SYNC must be brought low again. After the end of the serial
data transfer, data is automatically transferred from the input
shift register to the addressed register.
When the data has been transferred into the chosen register
of the addressed DAC, all DAC registers and outputs can be
updated by taking LDAC low.
相关PDF资料 |
PDF描述 |
|---|---|
| AD5764CSUZ | IC DAC 16BIT QUAD VOUT 32TQFP |
| AD5764RBSUZ | IC DAC 16BIT QUAD VOUT 32-TQFP |
| AD5781BRUZ-REEL7 | IC DAC 18BIT SRL 20TSSOP |
| AD5790BCPZ | IC DAC VOLT OUT 20BIT 24LFCSP |
| AD5791BRUZ | IC DAC 20BIT SRL 20TSSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5763CSUZ-TR | 制造商:Analog Devices 功能描述:16BIT +/-5V DUAL 1LSB - Tape and Reel |
| AD5764 | 制造商:AD 制造商全称:Analog Devices 功能描述:Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC |
| AD5764ASU | 制造商:AD 制造商全称:Analog Devices 功能描述:Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC |
| AD5764ASUZ | 功能描述:IC DAC 16BIT QUAD VOUT 32-TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 设置时间:4µs 位数:12 数据接口:串行 转换器数目:2 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 供应商设备封装:8-uMAX 包装:管件 输出数目和类型:2 电压，单极 采样率（每秒）:* 产品目录页面:1398 (CN2011-ZH PDF) |
| AD5764ASUZ-REEL7 | 功能描述:IC DAC 16BIT QUAD VOUT 32-TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
发布紧急采购，3分钟左右您将得到回复。