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| 型号： | AD5932YRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | IC PROG WAVEFORM GEN SNGL16TSSOP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 96 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 50MHz |
| 调节字宽（位）： | 24 b |
| 电源电压： | 2.3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 797 (CN2011-ZH PDF) |
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Data Sheet
AD5932
Rev. A | Page 17 of 28
SETTING UP THE FREQUENCY SCAN
As stated in the Frequency Profile section, the AD5932 requires
certain registers to be programmed to enable a frequency scan.
The Setting Up the Frequency Scan section discusses these
registers in more detail.
Start Frequency (FSTART)
To start a frequency scan, the user needs to tell the AD5932
what frequency to start scanning from. This frequency is stored
in a 24-bit register called FSTART. If the user wishes to alter the
entire contents of the FSTART register, two consecutive writes
must be performed: one to the LSBs and the other to the MSBs.
Note that for an entire write to this register, Control Bit B24
(D11) should be set to 1, with the LSBs programmed first.
In some applications, the user does not need to alter all 24 bits
of the FSTART register. By setting Control Bit B24 (D11) to 0, the
24-bit register operates as two 12-bit registers, one containing
the 12 MSBs and the other containing the 12 LSBs. This means
that the 12 MSBs of the FSTART word can be altered independently
of the 12 LSBs and vice versa. The addresses of both the LSBs
and the MSBs of this register are shown in the following bit map.
D15
D14
D13
D12
D11 to D0
1
0
12 LSBs of FSTART <11…0>
1
0
1
12 MSBs of FSTART <23…12>
Frequency Increments (Δf)
The value in the Δf register sets the increment frequency for the
scan and is added incrementally to the current output frequency.
Note that the increment frequency can be positive or negative,
thereby giving an increasing or decreasing frequency scan.
At the start of a scan, the frequency contained in the FSTART
register is output. Next, the frequency (FSTART + Δf ) is output.
This is followed by (FSTART + Δf + Δf), and so on. Multiplying
the Δf value by the number of increments (NINCR) and adding it
to the start frequency (FSTART) give the final frequency in the
scan. Mathematically, this final frequency/stop frequency is
represented by
FSTART + (NINCR × Δf)
The Δf register is a 23-bit register that requires two 16-bit writes
to be programmed. Table 7 gives the addresses associated with
both the MSB and LSB registers of the Δf word.
Table 7. Δf Register Bits
D15
D14
D13
D12
D11
D10 to D0
Scan
Direction
0
1
0
12 LSBs of
Δf
<11…0>
N/A
0
1
0
11 MSBs of
Δf
<22…12>
Positive
Δf
(FSTART +
Δf)
0
1
11 MSBs of
Δf
<22…12>
Negative
f
(FSTART
Δf)
Number of Increments (NINCR)
An end frequency is not required on the AD5932. Instead, this
end frequency is calculated by multiplying the frequency
increment value (Δf) by the number of frequency steps (NINCR)
and adding it to/subtracting it from the start frequency (FSTART);
that is, FSTART + NINCR × Δ f. The NINCR register is a 12-bit register,
with the address shown in the following bit map.
D15
D14
D13
D12
D11
D0
0
1
12 bits of NINCR
<11…0>
The number of increments is programmed in binary fashion,
with 000000000010 representing the minimum number of
frequency increments (two increments) and 111111111111
representing the maximum number of increments (4095).
Table 8. NINCR Data Bits
D11
…
D0
Number of Increments
0000
0010
Two frequency increments. This is the
minimum number of frequency
increments.
0000
0011
Three frequency increments.
0000
0100
Four frequency increments.
…
1111
1110
4094 frequency increments.
1111
4095 frequency increments.
Increment Interval (tINT)
The increment interval dictates the duration of the DAC output
signal for each individual frequency of the frequency scan. The
AD5932 offers the user two choices:
The duration is a multiple of cycles of the output frequency.
The duration is a multiple of MCLK periods.
The desired choice is selected by Bit D13 in the tINT register as
shown in the following bit map.
D15
D14
D13
D12
D11
D10 to D0
0
1
0
x
11 bits <10…0>
Fixed number of output
waveform cycles.
0
1
x
11 bits <10…0>
Fixed number of clock
periods.
Programming of this register is in binary form, with the
minimum number being decimal 2. Note that 11 bits, D10 to
D0, of the register are available to program the time interval. As
an example, if MCLK = 50 MHz, then each clock period/base
interval is (1/50 MHz) = 20 ns. If each frequency must be output
for 100 ns, then <00000000101> or decimal 5 must be pro-
grammed to this register. Note that the AD5930 can output each
frequency for a maximum duration of 211 1 (or 2047) times
the increment interval.
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相关代理商/技术参数 |
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| AD5932YRUZ-REEL7 | 功能描述:IC PROG WAVEFORM GENERAT 16TSSOP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD5933 | 制造商:AD 制造商全称:Analog Devices 功能描述:1 MSPS 12-Bit Impedance Converter, Network Analyzer |
| AD5933BRSZ-U1 | 制造商:Analog Devices 功能描述:CNVRTR NETWORK ANALYZER 16SSOP - Rail/Tube |
| AD5933YRSZ | 功能描述:IC NTWK ANALYZER 12B 1MSP 16SSOP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD5933YRSZ | 制造商:Analog Devices 功能描述:IC IMPEDANCE CONV 1MSPS 12BIT 16SSOP |
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