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参数资料
| 型号： | AD6622 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | 4通道，75 MSPS的数字传输信号处理器判刑 |
| 文件页数： | 3/28页 |
| 文件大小： | 242K |
| 代理商： | AD6622 |
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AD6622
–3–
REV. 0
TIMING CHARACTERISTICS
1
Test
Level
AD6622AS
Typ
Name
Parameter (Conditions)
Temp
Min
Max
Unit
CLK Timing Requirements
:
t
CLK
t
CLKL
t
CLKH
RESET
Timing Requirements
:
t
RESL
Input Wideband Data Timing Requirements
:
t
SI
Input to CLK Setup Time
t
HI
Input to CLK Hold Time
Parallel Output Switching Characteristics
:
t
SO
CLK to Output Setup Time
t
HO
CLK to Output Hold Time
t
ZO
Output Three-State Time
SYNC Timing Requirements
:
t
SS
SYNC to CLK Setup Time
t
HS
SYNC to CLK Hold Time
Serial Port Timing Requirements
:
t
DSCLK
CLK to SCLK Delay
t
DSDFS
SCLK to SDFS Delay
t
SSI
SDI to SCLK Setup Time
t
HSI
SDI to SCLK Hold Time
t
SCS
Serial Clock Skew
MICROPROCESSOR PORT, MODE INM (MODE = 0)
CLK Period
CLK Width Low
CLK Width High
Full
Full
Full
IV
IV
IV
13.3
5.5
5.5
ns
ns
ns
0.5
×
t
CLK
0.5
×
t
CLK
RESET
Width Low
Full
IV
30.0
ns
Full
Full
IV
IV
0.5
3.5
ns
ns
Full
Full
Full
IV
IV
V
12
ns
ns
ns
4.1
5
Full
Full
IV
IV
2.6
1.5
ns
ns
Full
Full
Full
Full
Full
V
IV
IV
IV
IV
8.5
ns
ns
ns
ns
ns
–1.2
8.5
5.5
+2.4
7
MODE INM Write Timing
:
t
HWR
t
SAM
t
HAM
t
DRDY
t
ACC
FAST
t
ACC
MEDIUM
t
ACC
SLOW
MODE INM Read Timing
:
t
SAM
t
HA
t
ZD
t
DD
t
DRDY
t
ACC
FAST
t
ACC
MEDIUM
t
ACC
SLOW
WR
(R/
W
) to RDY(
DTACK
) Hold Time
Address/Data to
WR
(R/
W
) Setup Time
Address/Data to RDY(
DTACK
) Hold Time
WR
(R/
W
) to RDY(
DTACK
) Delay
WR
(R/
W
) to RDY(
DTACK
) High Delay
WR
(R/
W
) to RDY(
DTACK
) High Delay
WR
(R/
W
) to RDY(
DTACK
) High Delay
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
0
0
0
ns
ns
ns
ns
ns
ns
ns
10.2
3
×
t
CLK
4
×
t
CLK
5
×
t
CLK
2
×
t
CLK
3
×
t
CLK
4
×
t
CLK
Address to
RD
(
DS
) Setup Time
Address to Data Hold Time
Data Three-State Delay
RDY(
DTACK
) to Data Delay
RD
(
DS
) to RDY(
DTACK
) Delay
RD
(
DS
) to RDY(
DTACK
) High Delay
RD
(
DS
) to RDY(
DTACK
) High Delay
RD
(
DS
) to RDY(
DTACK
) High Delay
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
0
0
3.4
ns
ns
ns
ns
ns
ns
ns
ns
7
10.5
t
CLK
– 10
10.2
3
×
t
CLK
4
×
t
CLK
5
×
t
CLK
2
×
t
CLK
3
×
t
CLK
4
×
t
CLK
(C
LOAD
= 40 pF, all outputs unless specified)
相关PDF资料 |
PDF描述 |
|---|---|
| AD6623 | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623ABC | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623AS | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623PCB | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6624AS | Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6622AS | 制造商:Analog Devices 功能描述:Transmit Signal Processor 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:4 CHANNEL 65 MSPS DIGITAL UPCONVERTER - Bulk |
| AD6622PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6622S/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6623 | 制造商:Analog Devices 功能描述: |
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