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参数资料
| 型号： | AD6622S |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | 4通道，75 MSPS的数字传输信号处理器判刑 |
| 文件页数： | 26/28页 |
| 文件大小： | 242K |
| 代理商： | AD6622S |
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AD6622
–26–
REV. 0
MULTIPLE TSP OPERATION
Each of the four Transmit Signal Processors (TSPs) of the
AD6622 can adequately reject the interpolation images of nar-
row bandwidth carriers such as AMPS, IS-136, GSM, EDGE,
and PHS. Wider bandwidth carriers such as IS-95 and UMTS
require a coordinated effort of multiple processing channels.
This section demonstrates how to coordinate multiple TSPs
to create wider bandwidth channels without sacri
fi
cing image
rejection. As an example, a UMTS carrier is modulated using
four TSPs (an entire AD6622). The same principals can be
applied to different designs using more or fewer TSPs. This sec-
tion does not explore techniques for using multiple TSPs to
solve problems other than Serial Port or RCF throughput.
Designing
fi
lter coef
fi
cients and control settings for deinterleaved
TSPs is no harder than designing a
fi
lter for a single TSP. For
example, if four TSPs are to be used, simply divide the input data
rate by four and generate the
fi
lter as normal. For any design, a
better
fi
lter can always be realized by incrementing the number
of TSPs to be used. When it is time to program the TSPs, only
two small differences must be programmed. First each channel
is con
fi
gured with exactly the same
fi
lter, scalars, modes and
NCO frequency. Since each channel receives data at 1/4 the
data rate and in a staggered fashion, the Start Hold-Off Counters
must also be staggered (see Programming Multiple TSPs section
below). Second, the phase offset of each NCO must be set to
match the demultiplexed ratio (1/4 in this example). Thus the
phase offset should be set to 90 degrees (16384, which is 1/4
of a 16-bit register).
Determining the Number of TSPs to Use
There are three limitations of a single TSP that can be over-
come by deinterleaving an input stream into multiple TSPs:
Serial Port bandwidth, the time restriction to the RCF impulse
response length (N
RCF
), and the DMEM restriction to N
RCF
.
If the input sample rate is faster than the Serial Port can accept
data, the data can be deinterleaved into multiple Serial Ports.
Recalling from the Serial Port description, the SCLK frequency
(f
SCLK
) is determined by the equation below. To minimize the
number of processing channels, SCLK
DIVIDER
should be set
as low as possible to get the highest f
SCLK
that the serial data
source can accept.
f
f
SCLK
(
SCLK
CLK
DIVIDER
=
×
+
2
1
)
(23)
A minimum of 32 SCLK cycles are required to accept an input
sample, so the minimum number of TSPs (N
TSP
) due to limited
Serial Port bandwidth is a function of the input sample rate (f
IN
),
as shown by the equation below.
×
N
ceil
f
f
TSP
IN
SCLK
≥
32
(24)
For a sample UMTS system, we will assume f
CLK
= 61.44 MHz,
and the serial data source can drive data at 30.72 MBPS
(SCLK
DIVIDER
= 0). To achieve f
IN
= 3.84 MHz, the mini-
mum N
TSP
is 4. (This is TSP channels, not TSP ICs.)
Multiple TSPs are also required if the RCF does not have enough
time or DMEM space to calculate the required RCF
fi
lter. Recall-
ing the maximum N
TAPS
equation from the RCF description, are
three restrictions to the RCF impulse response length, N
RCF
.
Time
CMEM
Restriction
↓
Restriction
↓
2
N
L
L
RCF
RCF
≤
×
min
,
,
16
128
(25)
↑
DMEM
Restriction
where:
L
L
L
L
N
f
f
RCF
CIC
CIC
TSP
CLK
IN
=
×
×
=
×
5
2
Deinterleaving the input data into multiple TSPs will extend the
time restriction and may possibly extend the DMEM restriction,
but will not extend the CMEM restriction. Deinterleaving the
input stream to multiple TSPs divides the input sample rate to
each TSP by the number of TSPs used (N
TSP
). To keep the out-
put rate
fi
xed, L must be increased by a factor of N
CH
, which
extends the time restriction. This increase in L may be achieved
by increasing any one or more of L
RCF
, L
CIC5
, or L
CIC2
within their
normal limits. Achieving a larger L by increasing L
RCF
instead
of L
CIC5
or L
CIC2
, will relieve the DMEM restriction as well.
In a UMTS example, N
TSP
= 4, f
CLK
= 61.44 MHz, and f
IN
=
3.84 MHz, resulting in L = 64. Factoring L into L
RCF
= 8, L
CIC
=
8, and L
CIC2
= 1, results in a maximum N
RCF
= 32 due to the time
restriction. Figure 22 shows an example RCF impulse response
that has a frequency response as shown in Figure 23 from
0 Hz to 7.68 MHz (f
IN
×
L
RCF
/N
TSP
). The composite RCF and
CIC frequency response is shown in Figure 24, on the same fre-
quency scale. This
fi
gure demonstrates a good approximation to
a root-raised-cosine with a roll-off factor of 0.22, a pass-band
ripple of 0.1 dB, and a stopband ripple better than
–
65 dB until
the lobe of the
fi
rst image which peaks at
–
50 dB about 5.6 MHz
from the carrier center. This lobe could be reduced by shifting
more of the interpolation towards the RCF, but that would
sacri
fi
ce near-in performance. As shown, the
fi
rst image can easily
be rejected by an analog
fi
lter further up the signal path.
Scaling must be considered as normal with an interpolation
factor of L, to guarantee no overflow in the RCF, CIC, or NCOs.
The output level at the summation port should be calculated
using an interpolation factor of L/N
TSP
.
Programming Multiple TSPs
Con
fi
guring the TSPs for deinterleaved operation is straight-
forward. All of the Channel Registers and CMEM of each TSP
are programmed identically, except the Start Hold-Off Counters
and NCO Phase Offset.
In order to separate the input timing to each TSP, the Hold-
Off Counters must be used to start each TSP successively in
response to a common Start SYNC. The Start SYNC may origi-
nate from the SYNC pin or the Microport. Each subsequent
TSP must have a Hold-Off Counter value L/N
TSP
larger than its
predecessor
’
s. If the TSPs are located on cascaded AD6622s,
the Hold-Off Counters of the upstream device should be incre-
mented by an additional one.
In the UMTS example, L = 64 and N
TSP
= 4, so in order to
respond as quickly as possible to a Start SYNC, the Hold-Off
Counter values should be 1, 17, 33, and 49.
相关PDF资料 |
PDF描述 |
|---|---|
| AD6622 | Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6623 | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623ABC | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623AS | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| AD6623PCB | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6622S/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
| AD6623 | 制造商:Analog Devices 功能描述: |
| AD6623ABC | 制造商:Analog Devices 功能描述:Signal Processor 196-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:4 CHANNEL, 104 MSPS DIGITAL TSP - Bulk |
| AD6623ABCZ | 制造商:Analog Devices 功能描述:Signal Processor 196-Pin CSP-BGA |
| AD6623AS | 制造商:Analog Devices 功能描述:Signal Processor 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:4 CHANNEL, 104 MSPS DIGITAL TSP - Bulk |
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