REV. 0
AD6623
–31–
Common Function Registers (not associated with a particular channel)
Internal Address
Bit
AD6622 Compatible Description
AD6623 Extension = 0
1
6
–
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Offset Binary Outputs
1
0
Clip Wideband I/O
3
0x001
7
First Sync Only
3
6
Beam on Pin Sync
3
5
Hop on Pin Sync
3
4
Start on Pin Sync
3
3
Ch. D Sync0 Pin Enable
3
2
Ch. C Sync0 Pin Enable
3
1
Ch. B Sync0 Pin Enable
3
0
Ch. A Sync0 Pin Enable
3
0x002
23
–
0
Unused
0x003
15
–
0
Unused
AD6623 Extensions Description
AD6623 Extension = 1
1
No Change
Wideband Input Disable
3
Dual Output Enable
3
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
BIST Counter
1, 3
BIST Value (read only)
0x000
7
Channel Function Registers (0x1XX = Ch. A, 0x2XX = Ch. B, 0x3XX = Ch. C, 0x4XX = Ch. D)
Internal Address
Bit
AD6622 Compatible Description
AD6623 Extensions Description
Ch. A Start Sync Select
3
00: Sync0 (See 0x001)
01: Sync1
10: Sync2
11: Sync3
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
Ch. A Hop Sync Select
3
00: Sync0 (See 0x001 Hop)
01: Sync1
10: Sync2
11: Sync3
0x100
17
–
16
Unused
15
–
0
7
–
5
4
3
2
1
–
0
Ch. A Start Hold
–
Off Counter
3
Reserved
Ch. A NCO Amplitude Dither Enable
Ch. A NCO Phase Dither Enable
Ch. A NCO Clear Phase Accumulator on Sync
Ch. A NCO Scale
00:
–
6 dB
01:
–
12 dB
10:
–
18 dB
11:
–
24 dB
Ch. A NCO Frequency Value
3
Unused
0x101
0x102
0x103
31
–
0
17
–
16
applied to the Sync pin (Pin 62). See the Synchronization section
for detailed explanations of the different modes.
External Address 4 Sleep
Bits in this register determine how the chip is programmed and
enables the channels. The program bits (D7:D4) must be set high
to
allow programming of CMEM and DMEM for each channel.
Sleep bits (D3:D0) are used to activate or sleep channels. These
can
be used manually by the user to bring up a channel by simply
writing
the required channel high. These bits can also be used in conjunc-
tion with the Start and Sync signals available in External Address
5 to synchronize the channels. See the Synchronization section for a
detailed explanation of different modes.
External Address 3:0 (Data Bytes)
These registers return or accept the data to be accessed for a
read or write to internal addresses
INTERNAL COUNTER REGISTERS AND ON-CHIP RAM
AD6623 and AD6622 Compatibility
The AD6623 functionality is a superset of the AD6622 functionality.
The AD6623 is pin-compatible with AD6622.
AD6622 compatibility is selected when bit 7 of Internal Control
Register 0x000 is low. In this state, all AD6623 extended control
registers are cleared. While in the AD6622 mode the unused
AD6623 pins are three-stated.
Listed below is the mapping of internal AD6623 registers. AD6622
compatibility is selected by setting
0x000:7 low.
In this state, all
AD6623 extended control registers are cleared. Registers marked
as
“
Reserved
”
must be written low.