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参数资料
| 型号： | AD698SQ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/12页 |
| 文件大小： | 0K |
| 描述： | IC LVDT SGNL COND UNVRSL 24CDIP |
| 标准包装： | 1 |
| 类型： | 信号调节器 |
| 输入类型： | 电压 |
| 输出类型： | 电压 |
| 接口： | LVDT |
| 电流 - 电源： | 15mA |
| 安装类型： | 通孔 |
| 封装/外壳： | 24-CDIP（0.600"，15.24mm） |
| 供应商设备封装： | 24-CDIP |
| 包装： | 管件 |
AD698
REV. B
–11–
VOUT =
2
× R
S
RG + 1
×V
IN
Solving for VOUT/VIN = 400 and setting RG = 100
then:
RS = [400 – 1]
× R
G/2 = 19.95 k
Choose an oscillator amplitude that is in the range of 1 V to
3.5 V rms. For an input excitation level of 3 V rms, the output
signal from the amplifier gain stage will be 3.5 V rms
× 0.8 V or
2.4 V rms, which is in the acceptable range.
Since A/B is known, the value of R2, the output FS resistor may
be chosen by the formula:
VOUT = A/B × 500 A × R2
For a 10 V output at FS, with an A/B of 0.8; solve for R2.
R2 = 10 V [0.8
× 500 A] = 25.0 k
This will result in a VOUT of 10 V for a full-scale signal from the
bridge. The other components, C1, C2, C3, C4 may be selected
by following the guidelines on general device operation men-
tioned earlier.
If a gain trim is required, then a trim resistor can be used to ad-
just either R2 or RG. Bridge offsets should be adjusted by a trim
network on the OFFSET 1 and OFFSET 2 pins of the AD698.
R1
C1
C2
C3
R4
R3
C4
R2
1000pF
SIGNAL
REFERENCE
RL
VOUT
100nF
6.8F
–15V
+15V
100nF
6.8F
AB
C
D
PHASE
LAG/LEAD
NETWORK
13
16
15
14
24
23
22
21
20
19
18
17
12
11
10
9
8
1
2
3
4
7
6
5
AD698
–VS
EXC1
EXC2
LEV1
LEV2
FREQ1
BFILT1
BFILT2
–BIN
+BIN
–AIN
FREQ2
SIG REF
OFFSET2
OFFSET1
+VS
OUT FILT
FEEDBACK
SIG OUT
–ACOMP
AFILT2
AFILT1
+ACOMP
+AIN
A2
RS
A1
RS
RESISTORS,
INDUCTORS
OR CAPACITORS
RT
AB
CD
PHASE LEAD
RS
C
RS
RT
A
B
CD
PHASE LAG
C
PHASE LAG = Arc Tan (Hz RC);
PHASE LEAD = Arc Tan 1/(Hz RC)
WHERE R = RS// (RS + RT)
RG
DUAL
OP AMP
Figure 20. AD698 Interconnection Diagram for AC Bridge Applications
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