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| 型号： | AD7190BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 40/41页 |
| 文件大小： | 0K |
| 描述： | IC ADC 2CH 24BIT W/PGA 24TSSOP |
| 产品培训模块： | Weigh Scale Introduction |
| 设计资源： | Precision Weigh Scale Design Using AD7190 with Internal PGA (CN0102) |
| 特色产品： | AD7190 Sigma-Delta Converter |
| 标准包装： | 62 |
| 位数： | 24 |
| 采样率（每秒）： | 4.8k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 管件 |
| 输入数目和类型： | 2 个差分，双极；4 个伪差分，双极 |
| 产品目录页面： | 777 (CN2011-ZH PDF) |
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Data Sheet
AD7190
Rev. C | Page 7 of 40
TIMING CHARACTERISTICS
AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless
otherwise noted.
Table 2.
Parameter
Limit at TMIN, TMAX (B Version)
Unit
Conditions/Comments1, 2
t3
100
ns min
SCLK high pulse width
t4
100
ns min
SCLK low pulse width
READ OPERATION
t1
0
ns min
CS falling edge to DOUT/RDY active time
60
ns max
DVDD = 4.75 V to 5.25 V
80
ns max
DVDD = 2.7 V to 3.6 V
0
ns min
SCLK active edge to data valid delay4
60
ns max
DVDD = 4.75 V to 5.25 V
80
ns max
DVDD = 2.7 V to 3.6 V
10
ns min
Bus relinquish time after CS inactive edge
80
ns max
t6
0
ns min
SCLK inactive edge to CS inactive edge
t7
10
ns min
SCLK inactive edge to DOUT/RDY high
WRITE OPERATION
t8
0
ns min
CS falling edge to SCLK active edge setup time4
t9
30
ns min
Data valid to SCLK edge setup time
t10
25
ns min
Data valid to SCLK edge hold time
t11
0
ns min
CS rising edge to SCLK edge hold time
1
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2
3
These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4
The SCLK active edge is the falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
6
RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY
is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the
digital word can be read only once.
CIRCUIT AND TIMING DIAGRAMS
ISINK (1.6mA WITH DVDD = 5V,
100A WITH DVDD = 3V)
ISOURCE (200A WITH DVDD = 5V,
100A WITH DVDD = 3V)
1.6V
TO
OUTPUT
PIN
50pF
07640-
002
Figure 2. Load Circuit for Timing Characterization
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7190BRUZ | 制造商:Analog Devices 功能描述:IC, ADC, 24BIT, 4.8KSPS, TSSOP-24 |
| AD7190BRUZ-REEL | 功能描述:IC ADC 2CH 24BIT W/PGA 24TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD7190WBRUZ | 功能描述:24 Bit Analog to Digital Converter 2, 4 Input 1 Sigma-Delta 24-TSSOP 制造商:analog devices inc. 系列:- 包装:管件 零件状态:有效 位数:24 采样率（每秒）:4.8k 输入数:2，4 输入类型:差分，个伪差分 数据接口:SPI，DSP 配置:MUX-PGA-ADC 无线电 - S/H:ADC:- A/D 转换器数:1 架构:三角积分 参考类型:外部， 内部 电压 - 电源，模拟:5V 电压 - 电源，数字:2.7 V ~ 5.25 V 特性:PGA，温度传感器 工作温度:-40°C ~ 105°C 封装/外壳:24-TSSOP（0.173"，4.40mm 宽） 供应商器件封装:24-TSSOP 标准包装:1 |
| AD7190WBRUZ-RL | 制造商:Analog Devices 功能描述: |
| AD7191 | 制造商:AD 制造商全称:Analog Devices 功能描述:Pin-Programmable, Ultralow Noise, 24-Bit, Sigma-Delta ADC for Bridge Sensors |
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