参数资料
| 型号： | AD7191BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/21页 |
| 文件大小： | 0K |
| 描述： | IC ADC 2CH 24B SD 24TSSOP |
| 产品培训模块： | Weigh Scale Introduction |
| 设计资源： | Precision Weigh Scale Design Using AD7191 with Internal PGA (CN0118) |
| 标准包装： | 62 |
| 位数： | 24 |
| 采样率（每秒）： | 120 |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 管件 |
| 输入数目和类型： | 2 个差分，双极 |
| 产品目录页面： | 777 (CN2011-ZH PDF) |
AD7191
Rev. A | Page 6 of 20
TIMING CHARACTERISTICS
AVDD = 3 V to 5.25 V; DVDD = 2.7 V to 5.25 V; AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted.
Table 2.
Parameter1, 2
Limit at TMIN, TMAX (B Version)
Unit
Conditions/Comments
t3
100
ns min
SCLK high pulse width
t4
100
ns min
SCLK low pulse width
Read Operation
t1
0
ns min
PDOWN falling edge to DOUT/RDY active time
60
ns max
DVDD = 4.75 V to 5.25 V
80
ns max
DVDD = 2.7 V to 3.6 V
0
ns min
SCLK active edge to data valid delay4
60
ns max
DVDD = 4.75 V to 5.25 V
80
ns max
DVDD = 2.7 V to 3.6 V
10
ns min
Bus relinquish time after PDOWN inactive edge
80
ns max
t6
0
ns min
SCLK inactive edge to PDOWN inactive edge
t7
10
ns min
SCLK inactive edge to DOUT/RDY high
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V.
2 See Figure 3.
3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4 The SCLK active edge is the falling edge of SCLK.
5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number
is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the
true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
6
RDY returns high after a read of the ADC. The digital word can be read only once.
ISINK (1.6mA WITH DVDD = 5V,
100A WITH DVDD = 3V)
ISOURCE (200A WITH DVDD = 5V,
100A WITH DVDD = 3V)
1.6V
TO
OUTPUT
PIN
50pF
08
16
3-
00
2
Figure 2. Load Circuit for Timing Characterization
TIMING DIAGRAM
t1
t3
t2
t7
t6
t5
t4
PDOWN (I)
NOTES
1. I = INPUT, O = OUTPUT
DOUT/RDY (O)
SCLK (I)
08
16
3-
00
3
Figure 3. Read Cycle Timing Diagram
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