参数资料
| 型号： | AD7192BRUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 30/41页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT 2CH W/PGA 24-TSSOP |
| 产品培训模块： | Weigh Scale Introduction |
| 设计资源： | Precision Weigh Scale Design Using AD7192 with Internal PGA (CN0119) |
| 标准包装： | 62 |
| 位数： | 24 |
| 采样率（每秒）： | 4.8k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 管件 |
| 输入数目和类型： | 2 个差分，单极；2 个差分，双极；4 个伪差分，单极；4 个伪差分，双极 |
| 产品目录页面： | 777 (CN2011-ZH PDF) |
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AD7192
Rev. A | Page 35 of 40
ENABLE PARITY
The AD7192 also has a parity check function on chip that
detects 1-bit errors in the serial communications between the
ADC and the microprocessor. When the ENPAR bit in the
mode register is set to 1, parity is enabled. The contents of the
status register must be transmitted along with each 24-bit con-
version when the parity function is enabled. To append the
contents of the status register to each conversion read, the
DAT_STA bit in the mode register should be set to 1. For each
conversion read, the parity bit in the status register is pro-
grammed so that the overall number of 1s transmitted in the
24-bit data-word is even. Therefore, for example, if the 24-bit
conversion contains eleven 1s (binary format), the parity bit is
set to 1 so that the total number of 1s in the serial transmission
is even. If the microprocessor receives an odd number of 1s, it
knows that the data received has been corrupted.
The parity function detects only 1-bit errors. For example, two
bits of corrupt data can result in the microprocessor receiving an
even number of 1s. Therefore, an error condition is not detected.
CALIBRATION
The AD7192 provides four calibration modes that can be pro-
grammed via the mode bits in the mode register. These modes
are internal zero-scale calibration, internal full-scale calibration,
system zero-scale calibration, and system full-scale calibration.
A calibration can be performed at any time by setting the MD2
to MD0 bits in the mode register appropriately. A calibration
should be performed when the gain is changed. After each
conversion, the ADC conversion result is scaled using the ADC
calibration registers before being written to the data register.
The offset calibration coefficient is subtracted from the result
prior to multiplication by the full-scale coefficient.
To start a calibration, write the relevant value to the MD2 to
MD0 bits. The DOUT/RDY pin and the RDY bit in the status
register go high when the calibration is initiated. When the
calibration is complete, the contents of the corresponding
calibration registers are updated, the RDY bit in the status
register is reset, the DOUT/RDY pin returns low (if CS is low),
and the AD7192 reverts to idle mode.
During an internal zero-scale or full-scale calibration, the
respective zero input and full-scale input are automatically
connected internally to the ADC input pins. A system
calibration, however, expects the system zero-scale and system
full-scale voltages to be applied to the ADC pins before
initiating the calibration mode. In this way, errors external to
the ADC are removed.
From an operational point of view, treat a calibration like
another ADC conversion. A zero-scale calibration, if required,
must always be performed before a full-scale calibration. Set the
system software to monitor the RDY bit in the status register or
the DOUT/RDY pin to determine the end of calibration via a
polling sequence or an interrupt-driven routine.
With chop disabled, both an internal zero-scale calibration and
a system zero-scale calibration require a time equal to the
settling time, tSETTLE (4/fADC for the sinc4 filter and 3/fADC for the
sinc3 filter).
With chop enabled, an internal zero-scale calibration is not
needed because the ADC itself minimizes the offset continuously.
However, if an internal zero-scale calibration is performed, the
settling time, tSETTLE (2/fADC), is required to perform the
calibration. Similarly, a system zero-scale calibration requires a
time of tSETTLE to complete.
To perform an internal full-scale calibration, a full-scale input
voltage is automatically connected to the selected analog input
for this calibration. For a gain of 1, the time required for an
internal full-scale calibration is equal to tSETTLE. For higher gains,
the internal full-scale calibration requires a time of 2 × tSETTLE.
A full-scale calibration is recommended each time the gain of a
channel is changed to minimize the full-scale error.
A system full-scale calibration requires a time of tSETTLE. With
chop disabled, the zero-scale calibration (internal or system
zero-scale) should be performed before the system full-scale
calibration is initiated.
An internal zero-scale calibration, system zero-scale calibration,
and system full-scale calibration can be performed at any
output data rate. An internal full-scale calibration can be
performed at any output data rate for which the filter word,
FS[9:0], is divisible by 16, FS[9:0] being the decimal equivalent
of the 10-bit word written to Bit FS9 to Bit FS0 in the mode
register. Therefore, internal full-scale calibrations can be
performed at output data rates such as 10 Hz or 50 Hz when
chop is disabled. Using these lower output data rates results in
better calibration accuracy.
The offset error is, typically, 150 μV/gain. If the gain is changed,
it is advisable to perform a calibration. A zero-scale calibration
(an internal zero-scale calibration or a system zero-scale
calibration) reduces the offset error to the order of the noise.
The gain error of the AD7192 is factory calibrated at a gain of 1
with a 5 V power supply at ambient temperature. Following this
calibration, the gain error is 0.001%, typically, at 5 V. Table 23
shows the typical uncalibrated gain error for the different gain
settings.
Table 23. Typical Precalibration Gain Error vs. Gain
Gain
Precalibration Gain Error (%)
8
0.11
16
0.20
32
0.23
64
0.29
128
0.39
An internal full-scale calibration reduces the gain error to
0.001%, typically, when the gain is equal to 1. For higher gains,
the gain error post internal full-scale calibration is 0.003%,
typically when AVDD is equal to 5 V. When AVDD is less than
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