参数资料
型号: AD7266BSUZ-REEL7
厂商: Analog Devices Inc
文件页数: 19/29页
文件大小: 0K
描述: IC ADC 12BIT 3CHAN 2MSPS 32TQFP
设计资源: AD7266 SAR ADC in DC-Coupled Differential and Single-Ended Appls (CN0039)
标准包装: 500
位数: 12
采样率(每秒): 2M
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 2
功率耗散(最大): 33.6mW
电压电源: 模拟和数字
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 32-TQFP
供应商设备封装: 32-TQFP(7x7)
包装: 带卷 (TR)
输入数目和类型: 12 个单端,单极;6 个差分,单极;6 个伪差分,单极
AD7266
Rev. B | Page 25 of 28
In the example shown in Figure 46, the serial clock is taken
from the ESSI0 so the SCK0 pin must be set as an output,
SCKD = 1, while the SCK1 pin is set as an input, SCKD = 0. The
frame sync signal is taken from SC02 on ESSI0, so SCD2 = 1,
while on ESSI1, SCD2 = 0; therefore, SC12 is configured as an
input. The VDRIVE pin of the AD7266 takes the same supply
voltage as that of the DSP563xx. This allows the ADC to operate
at a higher voltage than its serial interface and therefore, the
DSP563xx, if necessary.
AD7266 TO DSP563xx
The connection diagram in Figure 46 shows how the AD7266
can be connected to the ESSI (synchronous serial interface) of
the DSP563xx family of DSPs from Motorola. There are two
on-board ESSIs, and each is operated in synchronous mode
(Bit SYN = 1 in CRB register) with internally generated word
length frame sync for both TX and RX (Bit FSL1 = 0 and
Bit FSL0 = 0 in CRB).
Normal operation of the ESSI is selected by making MOD = 0
in the CRB. Set the word length to 16 by setting Bit WL1 = 1
and Bit WL0 = 0 in CRA.
AD72661
SCLK
DSP563xx1
1ADDITIONAL PINS OMITTED FOR CLARITY.
SCK0
SC12
SRD1
SRD0
CS
DOUTA
DOUTB
VDRIVE
VDD
SC02
SCK1
04603-039
To implement the power-down modes on the AD7266, the
word length can be changed to 8 bits by setting Bit WL1 = 0 and
Bit WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1
so the frame sync is negative. It is imperative for signal
processing applications that the frame synchronization signal
from the DSP563xx provides equidistant sampling.
Figure 46. Interfacing the AD7266 to the DSP563xx
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