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参数资料
| 型号： | AD73311LARU |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Low Cost, Low Power CMOS General Purpose Analog Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封装： | TSSOP-20 |
| 文件页数： | 10/36页 |
| 文件大小： | 382K |
| 代理商： | AD73311LARU |
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REV. A
AD73311L
–10–
F
B
= 4kHz
FS
INIT
= DMCLK/8
a. Analog Antialias Filter Transfer Function
F
B
= 4kHz
FS
INIT
= DMCLK/8
SIGNAL TRANSFER FUNCTION
NOISE TRANSFER FUNCTION
b. Analog Sigma-Delta Modulator Transfer Function
F
B
= 4kHz FS
INTER
= DMCLK/256
c. Digital Decimator Transfer Function
F
B
= 4kHz FS
FINAL
= 8kHz
FS
INTER
= DMCLK/256
d. Final Filter LPF (HPF) Transfer Function
Figure 7. AD73311L ADC Frequency Responses
Decimation Filter
The digital
fi
lter used in the AD73311L carries out two impor-
tant functions. Firstly, it removes the out-of-band quantization
noise, which is shaped by the analog modulator and secondly, it
decimates the high frequency bitstream to a lower rate 15-bit word.
The antialiasing decimation
fi
lter is a sinc-cubed digital
fi
lter
that reduces the sampling rate from DMCLK/8 at the modula-
tor to an output rate at the SPORT of DMCLK/M (where M
depends on the sample rate setting
—
M = 256 @ 64 kHz; M =
512 @ 32 kHz, M = 1024 @ 16 kHz, M = 2048 @ 8 kHz), and
increases the resolution from a single bit to 15 bits. Its Z trans-
form is given as: [(1
–
Z
–
N
)/(1
–
Z
–
1
)]
3
where N is determined by
the sampling rate (N = 32 @ 64 kHz, N = 64 @ 32 kHz, N =
128 @ 16 kHz, N = 256 @ 8 kHz). This ensures a minimal
group delay of 25
μ
s at the 64 kHz sampling rate.
ADC Coding
The ADC coding scheme is in twos complement format (see
Figure 8). The output words are formed by the decimation
fi
lter, which grows the word length from the single-bit output of
the sigma-delta modulator to a 15-bit word, which is the 16-bit
transfer being used as a flag bit to indicate either control or data
in the frame.
V
INN
V
INP
V
REF
+ (V
REF
0.32875)
V
REF
V
REF
–
(V
REF
0.32875)
10...00
00...00
01...11
ADC CODE DIFFERENTIAL
V
INN
V
INP
V
REF
+ (V
REF
0.6575)
V
REF
V
REF
–
(V
REF
0.6575)
10...00
00...00
01...11
ADC CODE SINGLE-ENDED
ANALOG
INPUT
ANALOG
INPUT
Figure 8. ADC Transfer Function
Decoder Channel
The decoder channel consists of a digital interpolator, digital
sigma-delta modulator, a single bit digital-to-analog converter
(DAC), an analog smoothing
fi
lter and a programmable gain
ampli
fi
er with differential output.
DAC Coding
The DAC coding scheme is in twos complement format with
0x7FFF being full-scale positive and 0x8000 being full-scale
negative.
Interpolation Filter
The anti-imaging interpolation
fi
lter is a sinc-cubed digital
fi
lter
which up-samples the 16-bit input words from the SPORT
input rate of DMCLK/M (where M depends on the sample rate
setting
—
M = 256 @ 64 kHz; M = 512 @ 32 kHz, M = 1024 @
16 kHz, M = 2048 @ 8 kHz), to a rate of DMCLK/8 while
fi
ltering to attenuate images produced by the interpolation pro-
cess. Its Z transform is given as: [(1
–
Z
–
N
)/(1
–
Z
–
1
)]
3
where N is
determined by the sampling rate (N = 32 @ 64 kHz, N = 64 @
32 kHz, N = 128 @ 16 kHz, N = 256 @ 8 kHz). The DAC
receives 16-bit samples from the host DSP processor at a rate of
DMCLK/M. If the host processor fails to write a new value to
the serial port, the existing (previous) data is read again. The
data stream is
fi
ltered by the anti-imaging interpolation
fi
lter,
but there is an option to bypass the interpolator for the mini-
mum group delay con
fi
guration by setting the IBYP bit (CRE:5) of
Control Register E. The interpolation
fi
lter has the same charac-
teristics as the ADC
’
s antialiasing decimation
fi
lter.
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PDF描述 |
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| AD73311AR | Low Cost, Low Power CMOS General Purpose Analog Front End |
| AD73311ARS | Low Cost, Low Power CMOS General Purpose Analog Front End |
| AD73311LAR | Low Cost, Low Power CMOS General Purpose Analog Front End |
| AD73311L | Low Cost, Low Power CMOS General Purpose Analog Front End Processor(低成本，低功耗的CMOS通用双模拟前端处理器) |
| AD73311 | Low Cost, Low Power CMOS General Purpose Analog Front End Processor(低成本、低功耗、CMOS通用模拟前端处理器) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73311LARU-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP T/R |
| AD73311LARU-REEL7 | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP T/R |
| AD73311LARUZ | 功能描述:IC PROCESSOR FRONT END LP 20SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73311LARUZ-RL | 功能描述:IC PROCESSOR FRONT END LP 20SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73311LARUZ-RL7 | 功能描述:IC PROCESSOR FRONT END LP 20SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
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