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参数资料
| 型号： | AD73311LARU |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Low Cost, Low Power CMOS General Purpose Analog Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO20 |
| 封装： | TSSOP-20 |
| 文件页数： | 26/36页 |
| 文件大小： | 382K |
| 代理商： | AD73311LARU |
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REV. A
AD73311L
–26–
DIGITAL GROUND
ANALOG GROUND
Figure 38. Ground Plane Layout
Avoid running digital lines under the device for they will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD73311L to avoid noise coupling. The power
supply lines to the AD73311L should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply lines. Fast switching signals such
as clocks should be shielded with digital ground to avoid radiat-
ing noise to other sections of the board, and clock signals should
never be run near the analog inputs. Traces on opposite sides of
the board should run at right angles to each other. This will
reduce the effects of feedthrough through the board. A microstrip
technique is by far the best but is not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground planes while signals are placed
on the other side.
Good decoupling is important when using high speed devices.
All analog and digital supplies should be decoupled to AGND
and DGND respectively, with 0.1
μ
F ceramic capacitors in
parallel with 10
μ
F tantalum capacitors. To achieve the best
from these decoupling capacitors, they should be placed as close
as possible to the device, ideally right up against it. In systems
where a common supply voltage is used to drive both the AVDD
and DVDD of the AD73311, it is recommended that the system
’
s
AVDD supply be used. This supply should have the recom-
mended analog supply decoupling between the AVDD pins of
the AD73311L and AGND and the recommended digital sup-
ply decoupling capacitors between the DVDD pin and DGND.
DSP Programming Considerations
This section discusses some aspects of how the serial port of the
DSP should be con
fi
gured and the implications of whether Rx
and Tx interrupts should be enabled.
DSP SPORT Con
fi
guration
Following are the key settings of the DSP SPORT required for
the successful operation with the AD73311L:
Con
fi
gure for external SCLK.
Serial Word Length = 16 bits.
Transmit and Receive Frame Syncs required with every word.
Receive Frame Sync is an input to the DSP.
Transmit Frame Sync is an:
Input
—
in Frame Sync Loop-Back Mode
Output
—
in Nonframe Sync Loop-Back Mode.
Frame Syncs occur one SCLK cycle before the MSB of the
serial word.
Frame Syncs are active high.
DSP SPORT Interrupts
If SPORT interrupts are enabled, it is important to note that the
active signals on the frame sync pins do not necessarily corre-
spond with the positions in time of where SPORT interrupts are
generated.
On ADSP-218x processors, it is necessary to enable SPORT
interrupts and use Interrupt Service Routines (ISRs) to handle
Tx/Rx activity, while on the TMS320C5x processors it is pos-
sible to poll the status of the Rx and Tx registers, which means
that Rx/Tx activity can be monitored using a single ISR that
would ideally be the Tx ISR as the Tx interrupt will typically
occur before the Rx ISR.
DSP SOFTWARE CONSIDERATIONS WHEN
INTERFACING TO THE AD73311L
It is important when choosing the operating mode and hardware
con
fi
guration of the AD73311L to be aware of their implications
for DSP software operation. The user has the flexibility of choosing
from either FSLB or nonFSLB when deciding on DSP to AFE
connectivity. There is also a choice to be made between using
autobuffering of input and output samples or simply choosing to
accept them as individual interrupts. As most modern DSP engines
support these modes, this appendix will attempt to discuss these
topics in a generic DSP sense.
Operating Mode
The AD73311L supports two basic operating modes: Frame Sync
Loop Back (FSLB) and nonFSLB (see Interfacing section). As
described previously, FSLB has some limitations when used in
Mixed Mode but is very suitable for use with the autobuffering
feature that is offered on many modern DSPs. Autobuffering
allows the user to specify the number of input or output words
(samples) that are transferred before a speci
fi
c Tx or Rx SPORT
interrupt is generated. Given that the AD73311L outputs two
sample words per sample period, it is possible using autobuffering
to have the DSP
’
s SPORT generate a single interrupt on receipt
of the second of the two sample words. Additionally, both samples
could be stored in a data buffer within the data memory store.
This technique has the advantage of reducing the number of both
Tx and Rx SPORT interrupts to a single one at each sample
interval. The user also knows where each sample is stored. The
alternative is to handle a larger number of SPORT interrupts
(twice as many in the case of a single AD73311L) while also
having some status flags to indicate where each new sample
comes from (or is destined for).
Mixed-Mode Operation
To take full advantage of Mixed-Mode operation, it is necessary
to con
fi
gure the DSP/Codec interface in nonFSLB and to disable
autobuffering. This allows a variable numbers of words to be sent
to the AD73311L in each sample period
—
the extra words being
control words which are typically used to update gain settings in
adaptive control applications. The recommended sequence for
updating control registers in mixed-mode is to send the control
word(s)
fi
rst before the DAC update word.
It is possible to use Mixed-Mode operation when con
fi
gured in
FSLB, but it is necessary to replace the DAC update with a control
word write in each sample period which may cause some discon-
tinuity in the output signal due to a sample point being missed
and the previous sample being repeated. This however may be
acceptable in some cases as the effect may be masked by gain
changes, etc.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73311LARU-REEL | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP T/R |
| AD73311LARU-REEL7 | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin TSSOP T/R |
| AD73311LARUZ | 功能描述:IC PROCESSOR FRONT END LP 20SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73311LARUZ-RL | 功能描述:IC PROCESSOR FRONT END LP 20SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73311LARUZ-RL7 | 功能描述:IC PROCESSOR FRONT END LP 20SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
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