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参数资料
| 型号： | AD73322LARU |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 封装： | MO-153AE, TSSOP-28 |
| 文件页数： | 2/40页 |
| 文件大小： | 437K |
| 代理商： | AD73322LARU |
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REV. 0
–2–
AD73322L–SPECIFICATIONS
1
(AVDD = 3 V 10%; DVDD = 3 V 10%; DGND = AGND = 0 V, f
DMCLK
=
A, Y Versions
Parameter
Min
Typ
16.384 MHz, f
SAMP
= 8 kHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Max
Unit
Test Conditions/Comments
REFERENCE
REFCAP
Absolute Voltage, VREFCAP
REFCAP TC
REFOUT
Typical Output Impedance
Absolute Voltage, V
REFOUT
Minimum Load Resistance
Maximum Load Capacitance
INPUT AMPLIFIER
Offset
Maximum Output Swing
Feedback Resistance
Feedback Capacitance
ANALOG GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Gain Accuracy
Settling Time
Delay
ADC SPECIFICATIONS
Maximum Input Range at VIN
2, 3
1.08
1.2
50
1.32
V
ppm/
°
C 0.1
μ
F Capacitor Required from
REFCAP to AGND2
V
Unloaded
k
pF
130
1.2
1
100
1.08
1.32
±
1.0
1.578
50
100
mV
V
k
pF
Max Output Swing = (1.578/1.2)
×
VREFCAP
f
C
= 32 kHz
+1
–
1
5
±
1.0
1.0
0.5
Bits
%
μ
s
μ
s
Gain Step Size = 0.0625
Output Unloaded
Tap Gain Change of
–
FS to +FS
DAC Unloaded
Measured Differentially
Max Input = (1.578/1.2)
×
VREFCAP
Measured Differentially
1.578
–
2.85
1.0954
–
6.02
V p-p
dBm
V p-p
dBm
Nominal Reference Level at VIN
(0 dBm0)
Absolute Gain
PGA = 0 dB
Gain Tracking Error
Signal to (Noise + Distortion)
PGA = 0 dB
–
2.0
–
0.7
±
0.1
+0.5
dB
dB
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to
–
50 dBm0
Refer to TPC 1.
300 Hz to 3400 Hz; f
SAMP
= 8 kHz, PUIA = 0
300 Hz to 3400 Hz; f
SAMP
= 8 kHz, PUIA = 1
0 Hz to f
SAMP
/2; f
SAMP
= 8 kHz
70
78
79
77.5
dB
dB
dB
Total Harmonic Distortion
PGA = 0 dB
Intermodulation Distortion
Idle Channel Noise Crosstalk
ADC-to-DAC
–
86
–
61
–
72
–
107
–
75
dB
dB
dBm0
dB
300 Hz to 3400 Hz; f
SAMP
= 8 kHz
PGA = 0 dB
PGA = 0 dB
ADC Input Signal Level: 1.0 kHz, 0 dBm0
DAC Input at Idle
ADC1 Input Signal Level: 1.0 kHz, 0 dBm0
ADC2 Input at Idle. Input Amplifiers Bypassed
Input Amplifiers Included in Input Channel
PGA = 0 dB
Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
ADC-to-ADC
–
92
dB
–
93
0
–
65
dB
mV
dB
DC Offset
Power Supply Rejection
–
20
+20
Group Delay
4, 5
Input Resistance at PGA
2, 4, 6
DIGITAL GAIN TAP
Gain at Maximum Setting
Gain at Minimum Setting
Gain Resolution
Delay
Settling Time
25
20
μ
s
k
Input Amplifiers Bypassed
+1
–
1
16
25
100
Bits
μ
s
μ
s
Tested to 5 MSBs of Settings
Includes DAC Delay
Tap Gain Change from
–
FS to +FS; Includes
DAC Settling Time
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73322LARU-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin TSSOP T/R 制造商:Rochester Electronics LLC 功能描述:SPEECH AND TELEPHONY CODEC I.C. - Tape and Reel |
| AD73322LARUZ | 功能描述:IC PROCESSOR FRONTEND DL 28TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73322LARUZ-REEL | 功能描述:IC PROCESSOR FRONTEND DL 28TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73322LARZ | 功能描述:IC ANALOG FRONT END DUAL 28-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73322LARZ-REEL | 制造商:Analog Devices 功能描述:DUAL-CHANNEL, 3 V FRONT-END PROCESSOR FOR GENERAL PURPOSE - Tape and Reel |
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