- 您现在的位置：买卖IC网 > PDF目录373897 > AD73322LARU (ANALOG DEVICES INC) Low Cost, Low Power CMOS General-Purpose Dual Analog Front End PDF资料下载
参数资料
| 型号： | AD73322LARU |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 通信及网络 |
| 英文描述： | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO28 |
| 封装： | MO-153AE, TSSOP-28 |
| 文件页数： | 21/40页 |
| 文件大小： | 437K |
| 代理商： | AD73322LARU |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页
REV. 0
AD73322L
–21–
OPERATION
Resetting the AD73322L
The
RESET
pin resets all the control registers. All registers are
reset to zero, indicating that the default SCLK rate (DMCLK/
8) and sample rate (DMCLK/2048) are at a minimum to ensure
that slow speed DSP engines can communicate effectively. As
well as resetting the control registers using the
RESET
pin, the
device can be reset using the RESET bit (CRA:7) in Control
Register A. Both hardware and software resets require four
DMCLK cycles. On reset, DATA/
PGM
(CRA:0) is set to 0
(default condition) thus enabling Program Mode. The reset
conditions ensure that the device must be programmed to the
correct settings after power-up or reset. Following a reset, the
SDOFS will be asserted 2048 DMCLK cycles after
RESET
going high. The data that is output following reset and during
Program Mode is random and contains no valid information
until either data or mixed mode is set.
Power Management
The individual functional blocks of the AD73322L can be
enabled separately by programming the power control register
CRC. It allows certain sections to be powered down if not
required, which adds to the device
’
s flexibility in that the user
need not incur the penalty of having to provide power for a
certain section if it is not necessary to their design. The power
control registers provide individual control settings for the major
functional blocks on each codec unit and also a global override
that allows all sections to be powered up by setting the bit.
Using this method the user could, for example, individually
enable a certain section, such as the reference (CRC:5), and
disable all others. The global power-up (CRC:0) can be used to
enable all sections, but if power-down is required using the
global control, the reference will still be enabled, in this case,
because its individual bit is set. Refer to Table XVI for details
of the settings of CRC.
NOTE: As both codec units share a common reference, the
reference control bits (CRC:5-7) in each SPORT are wire ORed
to allow either device to control the reference.
Operating Modes
There are three main modes of operation available on the
AD73322L; Program, Data and Mixed Program/Data modes.
Two other operating modes are typically reserved as diagnostic
modes: Digital and SPORT Loop-Back. The device configura-
tion
—
register settings
—
can be changed only in Program and
Mixed Program/Data Modes. In all modes, transfers of informa-
tion to or from the device occur in 16-bit packets, therefore the
DSP engine
’
s SPORT will be programmed for 16-bit transfers.
Program (Control) Mode
In Program Mode, CRA:0 = 0, the user writes to the control
registers to set up the device for desired operation
—
SPORT
operation, cascade length, power management, input/output
gain, etc. In this mode, the 16-bit information packet sent to the
device by the DSP engine is interpreted as a control word whose
format is shown in Table XII. In this mode, the user must address
the device to be programmed using the address field of the control
word. This field is read by the device and if it is zero (000 bin), the
device recognizes the word as being addressed to it. If the address
field is not zero, it is then decremented and the control word is
passed out of the device
—
either to the next device in a cascade or
back to the DSP engine. This 3-bit address format allows the
user to uniquely address any one of up to eight devices in a
cascade; please note that this addressing scheme is valid only
in sending control information to the device
—
a different format
is used to send DAC data to the device(s). As the AD73322L is
a dual codec, it features two separate device addresses for pro-
gramming purposes. If the AD73322L is used in a standalone
configuration connected to a DSP, the two device addresses
correspond to 0 and 1. If, on the other hand, the AD73322L
is configured in a cascade of multiple, dual or single codecs
(AD73322L or AD73311), its device addresses correspond with
its hardwired position in the cascade.
Following reset, when the SE pin is enabled, the codec responds
by raising the SDOFS pin to indicate that an output sample event
has occurred. Control words can be written to the device to
coincide with the data being sent out of the SPORT, as shown in
Figure 11, or they can lag the output words by a time interval
that should not exceed the sample interval. After reset, output
frame sync pulses will occur at a slower default sample rate,
which is DMCLK/2048, until Control Register B is programmed,
after which the SDOFS pulses will be set according to the contents
of DIR0-1. This is to allow slow controller devices to establish
communication with the AD73322L. During Program Mode,
the data output by the device is random and should not be
interpreted as ADC data.
SAMPLE WORD (DEVICE 2)
SE
SDOFS
SCLK
SDO
SDIFS
SDI
SAMPLE WORD (DEVICE 1)
CONTROL WORD (DEVICE 2)
CONTROL WORD (DEVICE 1)
Figure 11. Interface Signal Timing for Control Mode
Operation
Data Mode
Once the device has been configured by programming the cor-
rect settings to the various control registers, the device may exit
Program Mode and enter Data Mode. This is done by program-
ming the DATA/
PGM
(CRA:0) bit to a 1 and MM (CRA:1) to
0. Once the device is in Data Mode, the 16-bit input data frame
is now interpreted as DAC data rather than a control frame. This
data is therefore loaded directly to the DAC register. In Data
Mode, see Figure 12, as the entire input data frame contains
DAC data, the device relies on counting the number of input
frame syncs received at the SDIFS pin. When that number
equals the device count stored in the device count field of CRA,
the device knows that the present data frame being received is
its own DAC update data. When the device is in normal Data
Mode (i.e., mixed mode disabled), it must receive a hardware
reset to reprogram any of the control register settings.
相关PDF资料 |
PDF描述 |
|---|---|
| AD73322AR | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| AD73322AST | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| AD73322LAR | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| AD73322LAST | Low Cost, Low Power CMOS General-Purpose Dual Analog Front End |
| AD73322EB | Low Power 10MHz Current Feedback Amplifier; Package: SO; No of Pins: 8; Temperature Range: 0°C to +70°C |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD73322LARU-REEL | 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 28-Pin TSSOP T/R 制造商:Rochester Electronics LLC 功能描述:SPEECH AND TELEPHONY CODEC I.C. - Tape and Reel |
| AD73322LARUZ | 功能描述:IC PROCESSOR FRONTEND DL 28TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73322LARUZ-REEL | 功能描述:IC PROCESSOR FRONTEND DL 28TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73322LARZ | 功能描述:IC ANALOG FRONT END DUAL 28-SOIC RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD73322LARZ-REEL | 制造商:Analog Devices 功能描述:DUAL-CHANNEL, 3 V FRONT-END PROCESSOR FOR GENERAL PURPOSE - Tape and Reel |
发布紧急采购，3分钟左右您将得到回复。