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参数资料
| 型号： | AD7346B |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
| 中文描述： | 2对/ 1对ETSI兼容HDSL模拟前端 |
| 文件页数： | 6/8页 |
| 文件大小： | 93K |
| 代理商： | AD7346B |
AD5011
–6–
REV PrA
PRELIMINARY TECHNICAL DATA
PIN DESCRIPT ION
Mnemonic
Function
POWE R SUPPLY
V D R IV E
A G N D
A G N D
D V D D
D G N D
Digital output drive level.
Analog power supply.
Analog Ground.
Positive power supply for the digital section.
Digital Ground.
T RANSMIT CHANNE L
T xD A T A
T xSY N C
T xC L K
T xD E C OU P
T ransmit data input.
T ransmit data frame synchronization, logic input.
T ransmit serial clock, logic input.
T ransmit DAC reference decoupling pin. T he reference which supplies the DAC needs some
external decoupling.
Differential line driver positive output.
Differential line driver negative output.
D R V -OU T P
D R V -OU T N
E X T E RNAL INT E RFACE
SPIC L K
T F S
D T
D R
R E SE T B
PW R D W N B
Serial interface clock, logic input.
Serial Interface frame synchronisation, logic input.
Serial interface data input.
Serial interface data output.
Master Reset. T his is an active low logic input.
Master powerdown. When PWRDWNB is taken low, the complete AD5011 device is placed in a
sleep mode.
Filter tuning clock. T he clock for the filter tuning circuit in both the transmit and receive paths is
supplied to FCLK . A 16.384 MHz should be connected to this pin to obtain the specified
frequencies.
T est Mode. When T EST is tied to DVDD, the AD5011 is placed in a test mode. For normal
operation, this pin should be tied to DGND.
F C L K
T E ST
RE CE IVE CHANNE L
H Y BIN-2B
H Y BIN-2A
H Y BIN-1B
H Y BIN-1A
F IL T OU T P
F IL T OU T N
AD C IN P
A D C IN N
C AP-T
Hybrid non-inverting input.
Hybrid inverting input.
Hybrid inverting input.
Hybrid non-inverting input.
Positive differential output of the antialiasing filter.
Negative differential output of the antialiasing filter.
Positive differential input to the ADC.
Negative differential input to the ADC.
Receive ADC reference decoupling pin. T he reference which supplies the ADC needs some external
decoupling.
Receive ADC reference decoupling pin. T he reference which supplies the ADC needs some external
decoupling.
Voltage Reference. T he external reference is applied to this pin.
Reference common.
C ommon mode level.
ADC Sample clock, logic input. T his clock also operates as the frame synchronization.
ADC serial interface clock, logic input.
ADC serial data out.
C AP-B
V R E F
R E F -C OM
C OM -L V L
AD C C L K
SC L K
S D O
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD734AN | 功能描述:IC MULTIPLIER/DIVIDER 14-DIP RoHS:否 类别:集成电路 (IC) >> 线性 - 模拟乘法器，除法器 系列:- 标准包装:25 系列:HA 功能:模拟乘法器 位元/级数:四象限 封装/外壳:16-CDIP（0.300"，7.62mm） 供应商设备封装:16-CDIP 侧面铜焊 包装:管件 |
| AD734ANZ | 功能描述:IC MULT/DIV 4-QUADRANT 14-DIP RoHS:是 类别:集成电路 (IC) >> 线性 - 模拟乘法器，除法器 系列:- 标准包装:25 系列:HA 功能:模拟乘法器 位元/级数:四象限 封装/外壳:16-CDIP（0.300"，7.62mm） 供应商设备封装:16-CDIP 侧面铜焊 包装:管件 |
| AD734AQ | 功能描述:IC MULTIPLIER/DIVIDER 14CDIP RoHS:否 类别:集成电路 (IC) >> 线性 - 模拟乘法器，除法器 系列:- 标准包装:25 系列:HA 功能:模拟乘法器 位元/级数:四象限 封装/外壳:16-CDIP（0.300"，7.62mm） 供应商设备封装:16-CDIP 侧面铜焊 包装:管件 |
| AD734AQ TUBE | 制造商:Analog Devices 功能描述:MULTIPLIER 4 QUAD 0.4% 10MHZ DIP14 |
| AD734BN | 功能描述:IC MULTIPLIER/DIVIDER 14-DIP RoHS:否 类别:集成电路 (IC) >> 线性 - 模拟乘法器，除法器 系列:- 标准包装:25 系列:HA 功能:模拟乘法器 位元/级数:四象限 封装/外壳:16-CDIP（0.300"，7.62mm） 供应商设备封装:16-CDIP 侧面铜焊 包装:管件 |
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