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| 型号： | AD7352BRUZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/21页 |
| 文件大小： | 0K |
| 描述： | IC ADC DUAL 12BIT 3MSPS 16TSSOP |
| 设计资源： | DC-Coupled, Single-Ended-to-Differential Conversion Using AD8138 and AD7352 (CN0040) |
| 标准包装： | 2,500 |
| 位数： | 12 |
| 采样率（每秒）： | 3M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 45mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个差分，双极 |
AD7352
Rev. A | Page 10 of 20
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale (1 LSB below
the first code transition) and full scale (1 LSB above the last
code transition).
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Negative Full-Scale Error
Negative full-scale error is the deviation of the first code
transition (00 … 000) to (00 … 001) from the ideal (that is,
VREF + 0.5 LSB) after the midscale error has been adjusted out.
Negative Full-Scale Error Match
Negative full-scale error match is the difference in negative full-
scale error between the two ADCs.
Midscale Error
Midscale error is the deviation of the midscale code transition
(011 … 111) to (100 … 000) from the ideal (that is, 0 V).
Midscale Error Match
Midscale error match is the difference in midscale error
between the two ADCs.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code
transition (111 … 110) to (111 … 111) from the ideal (that is,
VREF 1.5 LSB) after the midscale error has been adjusted out.
Positive Full-Scale Error Match
Positive full-scale error match is the difference in positive full-
scale error between the two ADCs.
ADC-to-ADC Isolation
ADC-to-ADC isolation is a measure of the level of crosstalk
between ADC A and ADC B. It is measured by applying a full-
scale 1 MHz sine wave signal to one of the two ADCs and
applying a full-scale signal of variable frequency to the other
ADC. The ADC-to-ADC isolation is defined as the ratio of the
power of the 1 MHz signal on the converted ADC to the power
of the noise signal on the other ADC that appears in the FFT.
The noise frequency on the unselected channel varies from
100 kHz to 2.5 MHz.
Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency, fS. The frequency
of the input varies from 5 kHz to 25 MHz.
PSRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output
at full-scale frequency, f, to the power of a 100 mV p-p sine
wave applied to the common-mode voltage of VIN+ and VIN
of frequency, fS.
CMRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of a conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±0.5 LSB, after the end of a conversion.
Signal-to-(Noise and Distortion) Ratio (SINAD)
SINAD is the measured ratio of signal-to-(noise and distortion)
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise.
The theoretical SINAD for an ideal N-bit converter with a sine
wave input is given by
SINAD = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, SINAD is 74 dB and for a 14-bit
converter, SINAD is 86 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7352, it is defined as
()
1
6
5
4
3
2
V
THD
2
log
20
dB
+
=
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the rms value of the next largest component
in the ADC output spectrum (up to fS/2 and excluding dc) to
the rms value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried in
the noise floor, it is a noise peak.
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| AD7352YRUZ | 功能描述:IC ADC DUAL 12BIT 3MSPS 16TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
| AD7352YRUZ-500RL7 | 功能描述:IC ADC DUAL 12BIT 3MSPS 16TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD7352YRUZ-RL | 功能描述:IC ADC DUAL 12BIT 3MSPS 16TSSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD7356 | 制造商:AD 制造商全称:Analog Devices 功能描述:Differential Input,Dual,Simultaneous Sampling, 4.25 MSPS, 14-Bit, SAR ADC |
| AD7356_08 | 制造商:AD 制造商全称:Analog Devices 功能描述:Differential Input, Dual, Simultaneous Sampling, 5 MSPS, 12-Bit, SAR ADC |
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