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参数资料
| 型号： | AD7440BRMZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT DIFF IN 1MSPS 8MSOP |
| 标准包装： | 50 |
| 位数： | 10 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 9.25mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，单极 |
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AD7440/AD7450A
Rev. C | Page 23 of 28
MODES OF OPERATION
POWER-DOWN MODE
The operational mode of the AD7440/AD7450A is selected by
controlling the logic state of the CS signal during a conversion.
There are two possible modes of operation, normal and power-
down. The point at which
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of conversions. When the AD7440/AD7450A are in the
power-down mode, all analog circuitry is powered down. To
enter power-down mode, the conversion process must be
interrupted by bringing
CS is pulled high after the conversion
has been initiated determines whether or not the device enters
power-down mode. Similarly, if already in power-down, CS
controls whether the devices return to normal operation or
remain in power-down. These modes of operation are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for differing application requirements.
CS high anywhere after the second
falling edge of SCLK and before the 10th falling edge of SCLK,
as shown in Figure 42.
NORMAL MODE
This mode is intended for fastest throughput rate performance.
The user does not have to worry about any power-up times with
the AD7440/AD7450A remaining fully powered up all the time.
03051-A
-042
1
10
SCLK
SDATA
THREE-STATE
2
CS
Figure 41 shows the general diagram of the operation of the
AD7440/AD7450A in this mode. The conversion is initiated on
the falling edge of CS, as described in the Serial Interface
section. To ensure the part remains fully powered up,
Figure 42. Entering Power-Down Mode
CS must
remain low until at least 10 SCLK falling edges have elapsed
after the falling edge of
CS
Once
has been brought high in this window of SCLKs, the
part enters power-down, the conversion that was initiated by
the falling edge of
CS.
CS is terminated, and SDATA goes back into
three-state. The time from the rising edge of CS to SDATA
three-state enabled is never greater than t
03051-A
-041
110
CS
SCLK
SDATA
16
4 LEADING ZEROS + CONVERSION RESULT
8
(refer to the Timing
Specifications). If CS is brought high before the second SCLK
falling edge, the part remains in normal mode and does not
power down. This avoids accidental power-down due to glitches
on the CS line.
Figure 41. Normal Mode Operation
If CS
In order to exit this mode of operation and power up the
AD7440/AD7450A again, a dummy conversion is performed.
On the falling edge of
is brought high any time after the 10th SCLK falling edge,
but before the 16th SCLK falling edge, the part remains
powered up but the conversion terminates and SDATA goes
back into three-state. Sixteen serial clock cycles are required to
complete the conversion and access the complete conversion
result.
CS, the device begins to power up and
continues to power up as long as CS is held low until after the
falling edge of the 10th SCLK. The device is fully powered up
after 1 μs has elapsed and, as shown in
CS
Figure 43, valid data
results from the next conversion.
may idle high until the next conversion or may idle
low until sometime prior to the next conversion. Once a data
transfer is complete, when SDATA has returned to three-state,
another conversion can be initiated after the quiet time, tQUIET,
has elapsed by again bringing CS low.
03153-A
-031
CS
SCLK
SDATA
1
10
16
1
10
16
A
THIS PART IS FULLY POWERED
UP WITH VIN FULLY ACQUIRED
PART BEGINS
TO POWER UP
INVALID DATA
VALID DATA
tPOWER-UP
Figure 43. Exiting Power-Down Mode
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7440BRMZ2 | 制造商:AD 制造商全称:Analog Devices 功能描述:Differential Input, 1 MSPS ADCs in an 8-Lead SOT-23 |
| AD7440BRT | 制造商:AD 制造商全称:Analog Devices 功能描述:Differential Input, 1 MSPS ADCs in an 8-Lead SOT-23 |
| AD7440BRTR2 | 制造商:AD 功能描述:New |
| AD7440BRT-R2 | 制造商:Analog Devices 功能描述: |
| AD7440BRT-REEL7 | 制造商:Analog Devices 功能描述: |
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