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参数资料
| 型号： | AD7440BRMZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 28/29页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT DIFF IN 1MSPS 8MSOP |
| 标准包装： | 50 |
| 位数： | 10 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 9.25mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，单极 |
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AD7440/AD7450A
Rev. C | Page 7 of 28
TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of
Table 3. VDD = 2.7 V to 3.6 V, fSCLK = 18 MHz, fS = 1 MSPS, VREF = 2.0 V; VDD = 4.75 V to 5.25 V, fSCLK = 18 MHz, fS = 1 MSPS,
Parameter
Limit at TMIN, TMAX
Unit
Description
10
kHz min
18
MHz max
tCONVERT
16 × tSCLK
tSCLK = 1/fSCLK
888
ns max
tQUIET
60
ns min
Minimum quiet time between the end of a serial read and the next falling edge of CS
t1
10
ns min
Minimum CS pulse width
t2
10
ns min
CS falling edge to SCLK falling edge setup time
t33
20
ns max
Delay from CS falling edge until SDATA three-state disabled
t43
40
ns max
Data access time after SCLK falling edge
t5
0.4 tSCLK
ns min
SCLK high pulse width
t6
0.4 tSCLK
ns min
SCLK low pulse width
t7
10
ns min
SCLK edge to data valid hold time
t84
10
ns min
SCLK falling edge to SDATA three-state enabled
35
ns max
SCLK falling edge to SDATA three-state enabled
tPOWER-UP5
1
μs max
Power-up time from full power-down
1 Common-mode voltage.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V or 0.4 V or 2.0 V for VDD = 3 V.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the Timing Specifications is the true bus relinquish
time of the part and is independent of the bus loading.
5 See Power-Up Time section.
t3
t2
t4
t7
t8
t6
t1
t5
tQUIET
tCONVERT
CS
SCLK
SDATA
4 LEADING ZEROS
THREE-STATE
12
3
4
5
13
14
15
16
0
DB11
DB10
DB2
DB1
DB0
B
03051-A
-002
Figure 2. AD7450A Serial Interface Timing Diagram
t3
t2
t4
t7
t8
t6
t1
t5
tQUIET
tCONVERT
CS
SCLK
SDATA
4 LEADING ZEROS
2 TRAILING ZEROS THREE-STATE
12
3
4
5
13
14
15
16
0
DB9
DB8
DB0
0
B
03051-A
-003
Figure 3. AD7440 Serial Interface Timing Diagram
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| AD7440BRMZ2 | 制造商:AD 制造商全称:Analog Devices 功能描述:Differential Input, 1 MSPS ADCs in an 8-Lead SOT-23 |
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| AD7440BRTR2 | 制造商:AD 功能描述:New |
| AD7440BRT-R2 | 制造商:Analog Devices 功能描述: |
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