参数资料
型号: AD7440BRTZ-R2
厂商: Analog Devices Inc
文件页数: 16/29页
文件大小: 0K
描述: IC ADC 10BIT W/DIFF INP SOT-23-8
标准包装: 1
位数: 10
采样率(每秒): 1M
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 9.25mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: SOT-23-8
供应商设备封装: SOT-23-8
包装: 标准包装
输入数目和类型: 1 个差分,单极
其它名称: AD7440BRTZ-R2DKR
AD7440/AD7450A
Rev. C | Page 22 of 28
Timing Example 1
Having FSCLK = 18 MHz and a throughput rate of 1 MSPS gives a
cycle time of
1/Throughput = 1/1,000,000 = 1 μs
A cycle consists of
t2 + 12.5(1/FSCLK) + tACQ = 1 μs
Therefore, if t2 = 10 ns
10 ns + 12.5(1/18 MHz) + tACQ = 1 μs
tACQ = 296 ns
This 296 ns satisfies the requirement of 290 ns for tACQ.
From Figure 40, tACQ comprises
2.5(1/FSCLK) + t8 + tQUIET
where t8 = 35 ns. This allows a value of 122 ns for tQUIET,
satisfying the minimum requirement of 60 ns.
Timing Example 2
Having FSCLK = 5 MHz and a throughput rate of 315 kSPS gives a
cycle time of
1/Throughput = 1/315,000 = 3.174 μs
A cycle consists of
t2 + 12.5(1/FSCLK) + tACQ = 3.174 μs
Therefore, if t2 is 10 ns
10 ns + 12.5(1/5 MHz) + tACQ = 3.174 μs
tACQ = 664 ns
This 664 ns satisfies the requirement of 290 ns for tACQ.
From Figure 40, tACQ comprises
2.5(1/FSCLK) + t8 + tQUIET
where t8 = 35 ns. This allows a value of 129 ns for tQUIET,
satisfying the minimum requirement of 60 ns.
As in this example and with other slower clock values, the signal
may already be acquired before the conversion is complete, but
it is still necessary to leave 60 ns minimum tQUIET between
conversions. In Timing Example 2, the signal should be fully
acquired at approximately Point C in Figure 40.
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