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参数资料
| 型号： | AD7475ARZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/25页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SERIAL LP 8SOIC |
| 标准包装： | 98 |
| 位数： | 12 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 10.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
| 输入数目和类型： | 1 个单端，单极 |
AD7475/AD7495
Rev. B | Page 21 of 24
MICROPROCESSOR INTERFACING
The serial interface on the AD7475/AD7495 allows the parts
to be directly connected to a range of many different micro-
processors. This section explains how to interface the AD7475/
AD7495 with some of the more common microcontroller and
DSP serial interface protocols.
AD7475/AD7495 TO TMS320C5X/C54X
The serial interface on the TMS320C5x/C54x uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7475/AD7495. The CS input allows easy interfacing
between the TMS320C5x/C54x and the AD7475/AD7495
without any glue logic required. The serial port of the
TMS320C5x/C54x is set up to operate in burst mode with
internal CLKX (Tx serial clock) and FSX (Tx frame sync).
The serial port control register (SPC) must have the following
setup: FO = 0, FSM = 1, MCM = 1, and TXM = 1. The format
bit, FO, may be set to 1 to set the word length to 8 bits, in order
to implement the power-down modes on the AD7475/AD7495.
The connection diagram is shown in Figure 28. Note that for
signal processing applications, it is imperative that the frame
synchronization signal from the TMS320C5x/C54x provide
equidistant sampling. The VDRIVE pin of the AD7475/AD7495
takes the same supply voltage as that of the TMS320C5x/C54x.
This allows the ADC to operate at a higher voltage than the
serial interface, that is, TMS320C5x/C54x, if necessary.
AD7475/AD7495*
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
CLKX
DR
FBX
FSR
SDATA
VDRIVE
VDD
TMS320C5x/C54x*
CLKR
01684-
B-
029
CS
Figure 28. Interfacing to the TMS320C5x/54x
AD7475/AD7495 TO ADSP-21XX
The ADSP-21xx family of DSPs is interfaced directly to the
AD7475/AD7495 without any glue logic required. The VDRIVE
pin of the AD7475/AD7495 takes the same supply voltage as
that of the ADSP-21xx. This allows the ADC to operate at a
higher voltage than the serial interface, that is, ADSP-21xx, if
necessary.
The SPORT control register should be set up as shown in Table 6.
Table 6.
SPORT Control Register Bits
Function
TFSW = RFSW = 1
Alternate framing
INVRFS = INVTFS = 1
Active low frame signal
DTYPE = 00
Right-justify data
SLEN = 1111
16-bit data words
ISCLK = 1
Internal serial clock
TFSR = RFSR = 1
Frame every word
IRFS = 0
ITFS = 1
To implement the power-down modes, SLEN should be set to
1001 to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 29. The ADSP-21xx
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode and the SPORT control register is set
up as described. The frame synchronization signal generated
on the TFS is tied to CS and, as with all signal processing
applications, equidistant sampling is necessary. However, in this
example, the timer interrupt is used to control the sampling rate
of the ADC and, under certain conditions, equidistant sampling
may not be achieved.
AD7475/AD7495*
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
DR
RFS
TFS
SDATA
VDRIVE
VDD
ADSP-21xx*
SCLK
01684-
B-
030
CS
Figure 29. Interfacing to the ADSP-21xx
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