参数资料
| 型号： | AD7609BSTZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 20/36页 |
| 文件大小： | 0K |
| 描述： | IC DAS W/ADC 18BIT 8CH 64LQFP |
| 标准包装： | 1,500 |
| 类型： | 数据采集系统（DAS），ADC |
| 分辨率（位）： | 18 b |
| 采样率（每秒）： | 200k |
| 数据接口： | DSP，MICROWIRE?，并联，QSPI?，串行，SPI? |
| 电压电源： | 模拟和数字 |
| 电源电压： | 2.3 V ~ 5 V，4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 带卷 (TR) |
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Data Sheet
AD7609
Rev. A | Page 27 of 36
Figure 6 shows the timing diagram for reading one channel of
data, framed by the CS signal, from the AD7609 in serial mode.
The SCLK input signal provides the clock source for the serial
read operation. CS goes low to access the data from the AD7609.
The falling edge of CS takes the bus out of three-state and
clocks out the MSB of the 18-bit conversion result. This MSB
is valid on the first falling edge of the SCLK after the CS falling
edge. The subsequent 17 data bits are clocked out of the
AD7609 on the SCLK rising edge. Data is valid on the SCLK
falling edge. Eighteen clock cycles must be provided to the
AD7609 to access each conversion result.
The FRSTDATA output signal indicates when the first channel,
V1, is being read back. When the CS input is high, the FRSTDATA
output pin is in three-state. In serial mode, the falling edge of
CS takes FRSTDATA out of three-state and sets the FRSTDATA
pin high indicating that the result from V1 is available on the
DOUTA output data line. The FRSTDATA output returns to a
logic low following the 18th SCLK falling edge. If all channels
are read on DOUTB, the FRSTDATA output does not go high
when V1 is being output on this serial data output pin. It only
goes high when V1 is available on DOUTA (and this is when V5
is available on DOUTB).
READING DURING CONVERSION
Data can be read from the AD7609 while BUSY is high
and conversions are in progress. This has little effect on the
performance of the converter and allows a faster throughput
rate to be achieved. A parallel or serial read can be performed
during conversions and when oversampling may or may not
be in use. Figure 3 shows the timing diagram for reading while
BUSY is high in parallel or serial mode. Reading during conver-
sions allows the full throughput rate to be achieved when using
the serial interface with a VDRIVE of 3.3 V to 5.25 V.
Data can be read from the AD7609 at any time other than on
the falling edge of BUSY because this is when the output data
registers are updated with the new conversion data. t6, outlined
in Table 3, should be observed in this condition.
V1
V4
V2
V3
V5
V8
V6
V7
SCLK
DOUTA
DOUTB
CS
72
09760-
041
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