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参数资料
| 型号： | AD7609BSTZ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | 8-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP64 |
| 封装： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件页数： | 16/35页 |
| 文件大小： | 1737K |
| 代理商： | AD7609BSTZ |
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Preliminary Technical Data
AD7609
Rev. PrD | Page 23 of 35
Analog Input Antialiasing Filter
An analog antialiasing filter is also provided on the AD7609.
The filter is a second-order Butterworth. Figure 36 and
Figure 37 show the frequency and phase response respectively
of the analog antialiasing filter. In the ±5 V range, the 3 dB
frequency is typically 22 kHz. In the ±10 V range, the 3 dB
frequency is typically 32 kHz.
–40
–35
–30
–25
–20
–15
–10
–5
0
100
1k
10k
100k
A
TT
E
N
U
A
TIO
N
(
d
B
)
FREQUENCY (Hz)
10V DIFF
5V DIFF
09
76
0-
0
32
10V
0.1dB
TEMP
3dB
–40°C 13,354Hz 33,520Hz
25°C 12,769Hz 32,397Hz
85°C 12,427Hz 31,177Hz
5V
–40°C 10,303Hz 24,365Hz
25°C
9619Hz 23,389Hz
85°C
9326Hz 22,607Hz
Figure 36. Analog Antialiasing Filter Frequency Response
09
76
0-
1
33
10
100k
10k
1k
PH
A
SE
D
E
L
A
Y
(s
)
INPUT FREQUENCY (Hz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
±5V RANGE
±10V RANGE
AVCC, VDRIVE = 5V
fSAMPLE = 200kSPS
TA = 25°C
Figure 37. Analog Antialiasing Filter Phase Response
Track-and-Hold Amplifiers
The track-and-hold amplifiers on the AD7609 allow the ADC to
accurately acquire an input sine wave of full-scale amplitude
to 18-bit resolution. The track-and-hold amplifiers sample
their respective inputs simultaneously on the rising edge of
CONVST x. The aperture time for track-and-hold (that is, the
delay time between the external CONVST x signal and the
track-and-hold actually going into hold) is well matched, by design,
across all eight track-and-holds on one device and from device
to device. This matching allows more than one AD7609 device
to be sampled simultaneously in a system.
The end of the conversion process across all eight channels is
indicated by the falling edge of BUSY; and it is at this point that the
track-and-holds return to track mode, and the acquisition time
for the next set of conversions begins.
The conversion clock for the part is internally generated, and
the conversion time for all channels is 4 μs on the AD7609. The
BUSY signal returns low after all eight conversions to indicate the
end of the conversion process. On the falling edge of BUSY, the
track-and-hold amplifiers return to track mode. New data can
be read from the output register via the parallel, parallel byte, or
serial interface after BUSY goes low; or, alternatively, data from
the previous conversion can be read while BUSY is high. Reading
data from the AD7609 while a conversion is in progress has no
effect on performance and allows a faster throughput to be
achieved. In parallel mode at VDRIVE > 3.3 V, the SNR is reduced
by ~1.5 dB when reading during a conversion.
ADC TRANSFER FUNCTION
The output coding of the AD7609 is twos complement. The
designed code transitions occur midway between successive
integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is
FSR/262,144 for the AD7609. The ideal transfer characteristic
for the AD7609 is shown in Figure 38.
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
–FS + 1/2LSB
0V – 1LSB +FS – 3/2LSB
A
DC
CO
DE
ANALOG INPUT
+FSR – (–FSR)
218
LSB =
IN ± (IN–)
5V
REF
2.5V
±5V CODE =
× 131,072 ×
IN ± (IN–)
10V
REF
2.5V
±10V CODE =
× 131,072 ×
09
76
0-
03
4
Figure 38. AD7609 Transfer Characteristic
The LSB size is dependent on the analog input range selected
(see Table 7).
Table 7. Output Codes and Ideal Input Values
Description
Analog Input
(V+ (V)
10 V Range
Analog
Input
V+ (V)
5 V Range
Digital
Output
Code Hexa
FSR 0.5 LSB
+19.999847 V
9.999961 V
0x7FFF
Midscale + 1 LSB
+152.58 μV
76 μV
0x0001
Midscale
0 V
0x0000
Midscale 1LSB
152.58 μV
76 μV
0xFFFF
FSR + 1.5LSB
19.99977 V
9.99988 V
0x8001
FSR
20 V
10 V
0x8000
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