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参数资料
| 型号： | AD7609BSTZ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | 8-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP64 |
| 封装： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件页数： | 33/35页 |
| 文件大小： | 1737K |
| 代理商： | AD7609BSTZ |
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Preliminary Technical Data
AD7609
Rev. PrD | Page 7 of 35
TIMING SPECIFICATIONS
AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/ internal reference, TA = TMIN to TMAX, unless otherwise
noted.1
Table 3.
Limit at TMIN, TMAX
Parameter
Min
Typ
Max
Unit
Description
PARALLEL/SERIAL/BYTE MODE
tCYCLE
1/throughput rate
5
μs
Parallel mode, reading during or after conversion; or serial mode: VDRIVE =
4.75 V to 5.25 V, reading during a conversion using DOUTA and DOUTB lines
5
μs
Serial mode reading during conversion; VDRIVE = 3.3 V
10.5
μs
Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines
tCONV
Conversion time
3.45
4
4.15
μs
Oversampling off
7.87
9.1
μs
Oversampling by 2
16.05
18.8
μs
Oversampling by 4
33
39
μs
Oversampling by 8
66
78
μs
Oversampling by 16
133
158
μs
Oversampling by 32
257
315
μs
Oversampling by 64
tWAKE-UP STANDBY
100
μs
STBY rising edge to CONVST x rising edge; power-up time from standby mode
tWAKE-UP SHUTDOWN
Internal Reference
30
ms
STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
External Reference
13
ms
STBY rising edge to CONVST x rising edge; power-up time from
shutdown mode
tRESET
50
ns
RESET high pulse width
tOS_SETUP
20
ns
BUSY to OS x pin setup time
tOS_HOLD
20
ns
BUSY to OS x pin hold time
t1
40
ns
CONVST x high to BUSY high
t2
25
ns
Minimum CONVST x low pulse
t3
25
ns
Minimum CONVST x high pulse
t4
0
ns
BUSY falling edge to CS falling edge setup time
t52
0.5
ms
Maximum delay allowed between CONVST A, CONVST B rising edges
t6
25
ns
Maximum time between last CS rising edge and BUSY falling edge
t7
25
ns
Minimum delay between RESET low to CONVST x high
PARALLEL/BYTE READ
OPERATION
t8
0
ns
CS to RD setup time
t9
0
ns
CS to RD hold time
t10
RD low pulse width
16
ns
VDRIVE above 4.75 V
21
ns
VDRIVE above 3.3 V
25
ns
VDRIVE above 2.7 V
32
ns
VDRIVE above 2.3 V
t11
15
ns
RD high pulse width
t12
22
ns
CS high pulse width (see
);
Figure 5 CS and RD linked
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