参数资料
型号: AD7634BCPZ
厂商: Analog Devices Inc
文件页数: 21/32页
文件大小: 0K
描述: IC ADC 18BIT BIPO PROGR 48-LFCSP
标准包装: 1
系列: PulSAR®
位数: 18
采样率(每秒): 670k
数据接口: 串行,并联
转换器数目: 1
功率耗散(最大): 225mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘,CSP
供应商设备封装: 48-LFCSP-VQ(7x7)
包装: 托盘
输入数目和类型: 1 个差分,单极;1 个差分,双极
AD7634
Data Sheet
Rev. B | Page 28 of 32
External Clock Data Read After/During Conversion
It is also possible to begin to read data after conversion and
continue to read the last bits after a new conversion is initiated.
This method allows the full throughput and the use of a slower
SDCLK frequency. Again, it is recommended to use a
discontinuous SDCLK whenever possible to minimize potential
incorrect bit decisions. For the different modes, the use of a slower
SDCLK, such as 20 MHz in warp mode, 15 MHz in normal mode,
and 13 MHz in impulse mode, can be used.
SDIN
SDOUT
D0
123
17
18
BUSY
EXT/INT = 1 INVSCLK = 0
CS
SDCLK
4
D2
D1
19
20
MODE[1:0] = 3
RD = 0
16
D17
D16
D15
X17
X16
21
X0
X2
X1
X17
X16
X15
Y17
Y16
t31
X*
t32
t16
t33
t34
t37
t35
t36
*A DISCONTINUOUS SDCLK IS RECOMMENDED.
0
640
6-
04
2
Figure 44. Slave Serial Data Timing for Reading (Read After Convert)
SDOUT
D0
123
BUSY
EXT/INT = 1
INVSCLK = 0
CS
SDCLK
17
D1
MODE[1:0] = 3
RD = 0
18
D17
D16
t31
t32
t16
t37
t35
t36
CNVST
X*
t27
*A DISCONTINUOUS SDCLK IS RECOMMENDED.
DATA = SDIN
06
40
6-
0
43
Figure 45. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
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