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参数资料
| 型号： | AD7654ASTZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT DUAL 2CH 48LQFP |
| 标准包装： | 2,000 |
| 系列： | PulSAR® |
| 位数： | 16 |
| 采样率（每秒）： | 500k |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 135mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个差分，单极 |
| 配用： | EVAL-AD7654CBZ-ND - BOARD EVALUATION FOR AD7654 |
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AD7654
Rev. B | Page 20 of 28
SERIAL INTERFACE
The AD7654 is configured to use the serial interface when the
SER/PAR is held high. The AD7654 outputs 32 bits of data,
MSB first, on the SDOUT pin. The order of the channels being
output is also controlled by A/B. When high, Channel A is
output first; when low, Channel B is output first. This data
is synchronized with the 32 clock pulses provided on the
SCLK pin.
MASTER SERIAL INTERFACE
Internal Clock
The AD7654 is configured to generate and provide the serial
data clock SCLK when the EXT/INT pin is held low. The
AD7654 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted if desired. The output data is valid
on both the rising and falling edge of the data clock. Depending
on RDC/SDIN input, the data can be read after each conversion
show the detailed timing diagrams of these two modes.
Usually, because the AD7654 is used with a fast throughput, the
master-read-during-convert mode is the most recommended
serial mode when it can be used. In this mode, the serial clock
and data toggle at appropriate instants, which minimizes
potential feedthrough between digital activity and the critical
conversion decisions. The SYNC signal goes low after the LSB
of each channel has been output. Note that in this mode, the
SCLK period changes because the LSBs require more time to
settle, and the SCLK is derived from the SAR conversion clock.
Note that in the master-read-after-convert mode, unlike in
other modes, the signal BUSY returns low after the 32 data bits
are pulsed out and not at the end of the conversion phase,
which results in a longer BUSY width. One advantage of using
this mode is that it can accommodate slow digital hosts because
the serial clock can be slowed down by using DIVSCLK[1:0]
inputs. Refer to Table 4 for the timing details.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7655 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 1 MSPS, Differential, Programmable Input PulSAR ADC |
| AD7655ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:LOW COST 4-CHANNEL 1 MSPS 16-BIT ADC - Bulk 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7655 LFSCP-48 |
| AD7655ACPRL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R |
| AD7655ACPZ | 功能描述:IC ADC 16BIT 4CH 48-LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:PulSAR® 标准包装:1 系列:microPOWER™ 位数:8 采样率（每秒）:1M 数据接口:串行，SPI? 转换器数目:1 功率耗散（最大）:- 电压电源:模拟和数字 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:24-VFQFN 裸露焊盘 供应商设备封装:24-VQFN 裸露焊盘（4x4） 包装:Digi-Reel® 输入数目和类型:8 个单端，单极 产品目录页面:892 (CN2011-ZH PDF) 其它名称:296-25851-6 |
| AD7655ACPZRL | 功能描述:IC ADC 16BIT 4CHAN 48LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:PulSAR® 标准包装:1,000 系列:- 位数:12 采样率（每秒）:300k 数据接口:并联 转换器数目:1 功率耗散（最大）:75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端，单极；1 个单端，双极 |
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