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参数资料
| 型号： | AD7699BCPZRL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 8CH 16BIT 500KSPS 20LFCSP |
| 标准包装： | 1,500 |
| 位数： | 16 |
| 采样率（每秒）： | 500k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 32mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 20-LFCSP-VQ |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 8 个单端，单极；4 个差分，单极；4 个差分，双极；4 个伪差分，双极 |
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AD7699
Data Sheet
Rev.
| Page 24 of 28
GENERAL TIMING WITH A BUSY INDICATOR
Figure 38 details the timing for all three modes: reading/writing
during conversion, after conversion, and spanning conversion.
Note that the gating item for both CFG and data readback is at
the end of conversion (EOC). As detailed previously, the data
access should occur up to safe data reading/writing time, tDATA.
If the full CFG word is not written to prior to EOC, it is
discarded and the current configuration remains.
At the EOC, if CNV is low, the busy indicator is enabled. In
addition, to generate the busy indicator properly, the host must
assert a minimum of 17 SCK falling edges to return SDO to
high impedance because the last bit of data on SDO remains
active. Unlike the case detailed in the General Timing Without
a Busy Indicator section, if the conversion result is not read out
fully prior to EOC, the last bit clocked out remains. If this bit is
low, the busy signal indicator cannot be generated because the
digital output requires a high impedance, or a bit remaining high,
to low transition for the interrupt input of the host. A good
example of this occurs when an SPI host sends 16 SCKs because
these are usually limited to 8-bit or 16-bit bursts, thus the LSB
remains. Because the transition noise of the AD7699 is 4 LSBs
peak to peak (or greater), the LSB is low 50% of the time. For
this interface, the SPI host needs to burst 24 SCKs, or a QSPI
interface can be used and programmed for 17 SCKs.
The SCK can idle high or low depending on the CPOL and
CPHA settings if SPI is used. A simple solution is to use CPOL
= CPHA = 1 (not shown) with SCK idling high.
tCYC
tCONV
tDATA
POWER
UP
END OF CONVERSION (EOC)
START OF CONVERSION
EOC
ACQUISITION
(n –1)
ACQUISITION
(n)
ACQUISITION
(n + 1)
ACQUISITION
(n + 2)
CONVERSION (n – 1)
CONVERSION (n)
CONVERSION (n + 1)
CONVERSION (n – 2)
READ/
W
R
IT
E
DUR
IN
G
CO
NV
ERT
READ/
W
R
IT
E
AF
T
E
R
CO
NVE
R
T
RE
A
D/
W
RI
T
E
SP
AN
NI
NG
CO
NVE
R
T
PHASE
CNV
DIN
SDO
DIN
SDO
DIN
SDO
SCK
07354-
036
NOTES
1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.
A TOTAL OF 17 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK
IS ENABLED, A TOTAL OF 31 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.
DATA (n – 2)
DATA
(n – 2)
DATA
(n – 1)
DATA
(n – 1)
DATA (n)
DATA (n + 1)
CFG (n)
CFG (n + 2)
CFG (n + 1)
CFG (n + 3)
XXX
DATA
(n – 2)
DATA
(n – 1)
DATA (n)
1
17/31
1
17/31
1
17/31
11
17/31
117/31
1
17/31
1
17/31
1
17/31
1
17/31
1
17/31
XXX
CFG (n)
CFG (n + 1)
CFG (n + 2)
DATA
(n – 2)
DATA
(n – 1)
DATA (n)
DATA (n + 1)
CFG (n)
CFG (n + 1)
CFG (n + 2)
CFG (n + 3)
Figure 38. General Interface Timing for the AD7699 With a Busy Indicator
B
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