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| 型号： | AD7710ARZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 31/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT DIFF INP 24-SOIC |
| 标准包装： | 1,000 |
| 位数： | 24 |
| 采样率（每秒）： | 1.03k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 45mW |
| 电压电源： | 模拟和数字，双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个差分，单极；2 个差分，双极 |
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REV. G
–8–
AD7710
Pin
Mnemonic
Function
19
TFS
Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial data
expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active after
TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data-word is written
to the part.
20
RFS
Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the
self-clocking mode, the SCLK and SDATA lines both become active after
RFS goes low. In the external
clocking mode, the SDATA line becomes active after
RFS goes low.
21
DRDY
Logic Output. A falling edge indicates that a new output word is available for transmission. The
DRDY pin
will return high upon completion of transmission of a full output word.
DRDY is also used to indicate when
the AD7710 has completed its on-chip calibration sequence.
22
SDATA
Serial Data. Input/output with serial data being written to either the control register or the calibration regis-
ters, and serial data being accessed from the control register, calibration registers, or the data register.
During an output data read operation, serial data becomes active after
RFS goes low (provided DRDY is low).
During a write operation, valid serial data is expected on the rising edges of SCLK when
TFS is low. The
output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs.
23
DVDD
Digital Supply Voltage, 5 V. DVDD should not exceed AVDD by more than 0.3 V in normal operation.
24
DGND
Ground Reference Point for Digital Circuitry.
Terminology Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale (not to be con-
fused with bipolar zero), a point 0.5 LSB below the first code
transition (000 . . . 000 to 000 . . . 001) and full scale, a point
0.5 LSB above the last code transition (111 . . . 110 to 111 . . .
111). The error is expressed as a percentage of full scale.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code transi-
tion (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage
(AIN(–) + VREF/GAIN – 3/2 LSBs). It applies to both unipolar
and bipolar analog input ranges.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-
ating in the unipolar mode.
Bipolar Zero Error
This is the deviation of the midscale transition (0111 . . . 111 to
1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) – 0.5 LSB)
when operating in the bipolar mode.
Bipolar Negative Full-Scale Error
This is the deviation of the first code transition from the ideal
AIN(+) voltage (AIN(–) – VREF/GAIN + 0.5 LSB) when operat-
ing in the bipolar mode.
Positive Full-Scale Overrange
Positive full-scale overrange is the amount of overhead available
to handle input voltages on AIN(+) input greater than AIN(–) +
VREF/GAIN (for example, noise peaks or excess voltages due to
system gain errors in system calibration routines) without intro-
ducing errors due to overloading the analog modulator or to
overflowing the digital filter.
Negative Full-Scale Overrange
This is the amount of overhead available to handle voltages on
AIN(+) below AIN(–) –VREF/GAIN without overloading the
analog modulator or overflowing the digital filter. Note that the
analog input will accept negative voltage peaks even in the uni-
polar mode provided that AIN(+) is greater than AIN(–) and
greater than VSS – 30 mV.
Offset Calibration Range
In the system calibration modes, the AD7710 calibrates its offset
with respect to the analog input. The offset calibration range
specification defines the range of voltages that the AD7710 can
accept and still calibrate offset accurately.
Full-Scale Calibration Range
This is the range of voltages that the AD7710 can accept in the
system calibration mode and still calibrate full scale correctly.
Input Span
In system calibration schemes, two voltages applied in sequence
to the AD7710’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
mum input voltages from zero- to full-scale that the AD7710 can
accept and still calibrate gain accurately.
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