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参数资料
| 型号： | AD7739 |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | ADC |
| 英文描述： | 8-Channel, High Throughput, 24-Bit Sigma-Delta ADC |
| 中文描述： | 8通道，高吞吐量，24位Σ-Δ模数转换器 |
| 文件页数： | 21/32页 |
| 文件大小： | 380K |
| 代理商： | AD7739 |
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AD7739
Bit
4
Rev. 0 | Page 21 of 32
Mnemonic
CLKDIS
Description
Master Clock Output Disable. When this bit is set to 1, the master clock is disabled from appearing at the
MCLKOUT pin and the MCLKOUT pin is in a high impedance state. This allows turning off the MCLKOUT as a
power saving feature. When using an external clock on MCLKIN, the AD7739 continues to have internal clocks
and will convert normally regardless of the CLKDIS bit state. When using a crystal oscillator or ceramic resonator
across the MCLKIN and MCLKOUT pins, the AD7739 clock is stopped and no conversions can take place when
the CLKDIS bit is active. The AD7739 digital interface can still be accessed using the SCLK pin.
Dump Mode. When this bit is reset to 0, the channel status register and channel data register will be addressed
and read separately. When the DUMP bit is set to 1, the channel status register will be followed immediately by
a
read of the channel data register regardless of whether the status or data register has been addressed through
the communications register. The continuous read mode will always be dump mode reading the channel status
and channel data registers, regardless of the DUMP bit value (see the Digital Interface Description section
for
details).
When this bit is set to 1, the AD7739 will operate in the continuous read mode (see the Digital Interface
Description section for details).
Channel Data Register Data Width Selection Bit. When set to 1, the channel data registers will be 24 bits wide.
When set to 0, the channel data registers will be 16 bits wide.
This bit determines the channel data register’s value when the analog input voltage is outside the nominal input
voltage range. When the CLAMP bit is set to 1, the channel data register will be digitally clamped to either all 0s
or all 1s when the analog input voltage goes outside the nominal input voltage range. When the CLAMP bit is
reset to 0, the data registers reflect the analog input voltage even outside the nominal voltage range (see the
Analog Input’s Extended Voltage Range section).
3
DUMP
2
Cont RD
1
24/16 BIT
0
CLAMP
MD2 MD1 MD0 Operating Mode Description
0
0
0
Idle
The default mode after power-on or reset. The AD7739 automatically returns to this mode after any
calibration or after a single conversion.
The AD7739 performs a conversion on the specified channel. After the conversion is complete, the
relevant channel data register and channel status register are updated, the relevant RDY bit in the
ADC status register is set, and the AD7739 continues converting on the next enabled channel. The
part will cycle through all enabled channels until it is put into another mode or reset. The cycle
period will be the sum of all enabled channels’ conversion times, set by the corresponding channel
conversion time registers.
The AD7739 performs a conversion on the specified channel. After the conversion is complete, the
relevant channel data register and channel status register are updated, the relevant RDY bit in the
ADC status register is set, the RDY pin goes low, the MD2–MD0 bits are reset, and the AD7739 returns
to idle mode. Requesting a single conversion ignores the channel setup register enable bits; a
conversion will be performed even if that channel is disabled.
The ADC and the analog front end (internal buffer) go into the power-down mode. The AD7739
digital interface can still be accessed. The CLKDIS bit works separately, and the MCLKOUT mode is not
affected by the power-down (standby) mode.
A zero-scale self-calibration is performed on internally shorted ADC inputs. After the calibration is
complete, the contents of the ADC zero-scale calibration register are updated, all RDY bits in the ADC
status register are set, the RDY pin goes low, the MD2–MD0 bits are reset, and the AD7739 returns to
idle mode.
A full-scale self-calibration is performed on an internally generated full-scale signal. After the
calibration is complete, the contents of the ADC full-scale calibration register are updated, all RDY
bits in the ADC status register are set, the RDY pin goes low, the MD2–MD0 bits are reset, and the
AD7739 returns to idle mode.
A zero-scale system calibration is performed on the selected channel. An external system zero-scale
voltage should be provided at the AD7739 analog input and this voltage should remain stable for the
duration of the calibration. After the calibration is complete, the contents of the corresponding
channel zero-scale calibration register are updated, all RDY bits in the ADC status register are set, the
RDY pin goes low, the MD2–MD0 bits are reset, and the AD7739 returns to idle mode.
A full-scale system calibration is performed on the selected channel. An external system full-scale
voltage should be provided at the AD7739 analog input and this voltage should remain stable for the
duration of the calibration. After the calibration is complete, the contents of the corresponding
channel full-scale calibration register are updated, all RDY bits in the ADC status register are set, the
RDY pin goes low, the MD2–MD0 bits are reset, and the AD7739 returns to idle mode.
0
0
1
Continuous
Conversion
0
1
0
Single
Conversion
0
1
1
Power-Down
(Standby)
1
0
0
ADC Zero-Scale
Self-Calibration
1
0
1
ADC Full-Scale
Self-Calibration
1
1
0
Channel Zero-
Scale System
Calibration
1
1
1
Channel Full-
Scale System
Calibration
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