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参数资料
| 型号： | AD7739 |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | ADC |
| 英文描述： | 8-Channel, High Throughput, 24-Bit Sigma-Delta ADC |
| 中文描述： | 8通道，高吞吐量，24位Σ-Δ模数转换器 |
| 文件页数： | 23/32页 |
| 文件大小： | 380K |
| 代理商： | AD7739 |
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AD7739
RESET
The AD7739 can be reset by the RESET pin or by writing a reset
sequence to the AD7739 serial interface. The reset sequence is
N × 0 + 32 × 1, which could be the data sequence 0x00 + 0xFF +
0xFF + 0xFF + 0xFF in a byte-oriented interface.
Rev. 0 | Page 23 of 32
The AD7739 also features a power-on reset with a trip point
of 2 V and goes to the defined default state after power-on.
It is the system designer’s responsibility to prevent an unwanted
write operation to the AD7739. The unwanted write operation
could happen when a spurious clock appears on the SCLK while
the CS pin is low. Note that if the AD7739 interface signals are
floating or undefined at system power-on, the part can be
inadvertently configured into an unknown state. This could be
easily overcome by initiating either a hardware reset event or a
32 ones reset sequence as the first step in the system
configuration.
ACCESS THE AD7739 REGISTERS
All communications to the part start with a write operation to
the communications register followed by either reading or
writing the addressed register. In a simultaneous read-write
interface (such as SPI), write 0 to the AD7739 while reading
data.
Figure 16 shows the AD7739 interface read sequence for the
ADC status register.
SINGLE CONVERSION AND READING DATA
When the mode register is being written, the ADC status byte
is cleared and the RDY pin goes high, regardless of its previous
state. When the single conversion command is written to the
mode register, the ADC starts the conversion on the channel
selected by the address of the mode register. After the
conversion is completed, the data register is updated, the mode
register is changed to idle mode, the relevant RDY bit is set,
and the RDY pin goes low. The RDY bit is reset and the RDY
pin returns high when the relevant channel data register is
being read.
Figure 17 shows the digital interface signals executing a single
conversion on Channel 0, waiting for the RDY pin to go low,
and reading the Channel 0 data register.
DUMP MODE
When the DUMP bit in the mode register is set to 1, the channel
status register will be read immediately by a read of the channel
data register, regardless of whether the status or the data register
has been addressed through the communications register. The
DIN pin should not be high while reading 24-bit data in dump
mode; otherwise, the AD7739 will be reset.
Figure 18 shows the digital interface signals executing a single
conversion on Channel 0, waiting for the RDY pin to go low,
and reading the Channel 0 status register and data register in
the dump mode.
DIN
SCLK
CS
DOUT
WRITE
COMMUNICATIONS
REGISTER
WRITE
MODE
REGISTER
RDY
CONVERSION TIME
READ DATA REGISTER
0x38
0x40
0x48
(0x00)
(0x00)
DATA
DATA
WRITE
COMMUNICATIONS
REGISTER
03742-0-017
Figure 17. Serial Interface Signals—Single Conversion Command and 16-Bit Data Reading
DIN
SCLK
CS
DOUT
WRITE
COMMUNICATIONS
REGISTER
WRITE
MODE
REGISTER
RDY
CONVERSION TIME
READ DATA
REGISTER
READ
CHANNEL
STATUS
0x38
0x48
0x48
WRITE
COMMUNICATIONS
REGISTER
(0x00)
(0x00)
(0x00)
STATUS
DATA
DATA
03742-0-018
Figure 18. Serial Interface Signals—Single Conversion Command, 16-Bit Data Reading, Dump Mode
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