参数资料
型号: AD7739BRU-REEL
厂商: ANALOG DEVICES INC
元件分类: ADC
英文描述: 8-Channel, High Throughput, 24-Bit Sigma-Delta ADC
中文描述: 8-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24
封装: MS-153AD, TSSOP-24
文件页数: 18/32页
文件大小: 380K
代理商: AD7739BRU-REEL
AD7739
CHANNEL ZERO-SCALE CALIBRATION REGISTERS
24 Bits, Read/Write Registers, Address 0x10–0x17,
Default Value 0x80 0000
Rev. 0 | Page 18 of 32
These registers hold the particular channel zero-scale
calibration coefficients. The value in these registers is used in
conjunction with the value in the corresponding channel full-
scale calibration register, the ADC zero-scale calibration
register, and the ADC full-scale calibration register to digitally
scale the particular channel conversion results. The value in this
register is updated automatically following the execution of a
channel zero-scale system calibration.
The format of the channel zero-scale calibration register is a
sign bit and a 22-bit unsigned value. Writing this register is
possible in the idle mode only (see the Calibration section
for details).
CHANNEL FULL-SCALE CALIBRATION REGISTERS
24 Bits, Read/Write Registers, Address 0x18–0x1F,
Default Value 0x20 0000
These registers hold the particular channel full-scale calibration
coefficients. The value in these registers is used in conjunction
with the value in the corresponding channel zero-scale
calibration register, the ADC zero-scale calibration register, and
the ADC full-scale calibration register to digitally scale the
particular channel conversion results. The value in this register
is updated automatically following the execution of a channel
full-scale system calibration. Writing this register is possible in
the idle mode only (see the Calibration section for details).
CHANNEL STATUS REGISTERS
8 Bits, Read-Only Registers, Address 0x20–0x27, Default Value 0x20 × Channel Number
These registers contain individual channel status information and some general AD7739 status information. Reading the status registers
can be associated with reading the data registers in the dump mode. Reading the status registers is always associated with reading the data
registers in the continuous read mode (see the Digital Interface Description section for details).
Bit
Mnemonic
Default
Bit 7
CH2
Bit 6
CH1
Bit 5
CH0
Bit 4
0/P0
0
Bit 3
RDY/P1
0
Bit 2
NOREF
0
Bit 1
SIGN
0
Bit 0
OVR
0
Channel Number
Bit
7–5
Mnemonic
CH2–CH0
Description
These bits reflect the channel number. This can be used for current channel identification and easier operation
of the dump mode and continuous read mode.
When the status option bit of the corresponding channel setup register is reset to 0, this bit is read as a 0.
When the status option bit is set to 1, this bit reflects the state of the P0 pin, whether it is configured as an
input or an output.
When the status option bit of the corresponding channel setup register is reset to 0, this bit reflects the
selected channel RDY bit in the ADC status register. When the status option bit is set to 1, this bit reflects the
state of the P1 pin, whether it is configured as an input or an output.
This bit indicates the reference input status. If the voltage between the REFIN(+) and REFIN(–) pins is less than
NOREF, the trigger voltage, and a conversion is executed, then the NOREF bit goes to 1.
This bit reflects the voltage polarity at the analog input. It will be 0 for a positive voltage and 1 for a negative
voltage.
This bit reflects either the overrange or the underrange on the analog input. The bit is set to 1 when the
analog input voltage goes over or under the nominal voltage range (see the Analog Input’s Extended Voltage
Range section).
4
0/P0
3
RDY/P1
2
NOREF
1
SIGN
0
OVR
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